MP2935DQK-LF-Z Datasheet, PDF (36/42 Pages) MPS Industries, Inc. – 4-Phase PWM Controller for VR12.5 Applications

MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Monitoring (VR_HOT#) and Temperature Zone
MP2935 provides a temperature sense pin TEMP
and VR_HOT# signal to indicate an over-
temperature event. VR_HOT# can be routed to
various system thermal management controllers.
VRHOT# pin is an open-drain output, active low
and can be used to drive the CPU’s force thermal
throttle input.
The ADC converts the V_TEMP voltage to update
the temperature zone register and compare this
value with VRHOT# trip threshold programmed in
the SVID register 22h.
For the ADC conversion, V_TEMP=0.9V equates to
64h stored in the register 17h.
MP2935 utilize Intelli-Phase’s^TM on-die
temperature sensing output to monitor the hottest
phase’s junction temperature. Simply connects
every Intelli-Phase’s^TM VTEMP pin to MP2935’s
TEMP. Connect a 1KΩ resistor from TEMP pin
to ground to sink the voltage when temperature is
going down.
VR_HOT# trip point is programmable by TMAX
pin. The hysteresis of VR_HOT# is around 3% of
the maximum temperature stored in the register
22h. The tolerance on VR_HOT# should be ± 4%
or approximately ±4°C at 100°C setting.
R_TMAX  250  TMAX
If the desire TMAX is 100^oC, then select 25KΩ
for R_TMAX.
Start up Sequence
MP2935 must strictly follow the start-up
sequence shown in Figure 13.
Figure 13 shows the diagrams of the start-up
sequence described below:
(1) VCC ramps up to 5V.
(2) VR controllers receive hardware enable,
i.e. EN is high. It takes 35µs (T1) from EN
high to VDD ramped to 3.3V.
(3) SVID bus exits Reset State when the
VDD is higher than its UVLO threshold.
The part is ready to accept SVID
command 1.6ms (T2) after VDD reached
3.3V.
(4) Soft-start begins (DAC output starts to
ramp up) 1.6ms (T2) after VDD reached
3.3V. VR ramps to the V_BOOT voltage with
slow slew rate. Once VR reached the
V_BOOT voltage, it asserts VR_SETTLE,
ALERT# and VR_RDY.⁽⁶⁾
(5) Start up sequence finished.
Notes:
6) CPU determines when the ALERT# signal is cleared. It may
clear ALERT# after the rail is up.
MP2935 Rev. 1.02
www.MonolithicPower.com
36
8/25/2015
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