NB6381DL-LF-Z Datasheet, PDF (14/19 Pages) MPS Industries, Inc. – High Efficiency, Fast Transient, 8A, 28V Synchronous Step-down Converter in a Tiny QFN20 (3x4mm) Package

NB6381–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
R₁
=
(V_OUT
−
V_REF
−
1
2
V_RAMP )
V_REF
+
1
2
V_RAMP
R₂
(17)
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47μF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
SW
L
Vo
FB ^{R4 C4}
Cdc
R1
Ceramic
R2
Figure 11—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous. Therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitors as close to the IN pin as
possible.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
I_CIN = I_OUT ×
V_{OUT × (1−} V_{OUT )}
V_IN
V_IN
(18)
The worst-case condition occurs at V_IN = 2V_OUT,
where:
I_CIN
=
I_OUT
2
(19)
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
The input voltage ripple can be estimated as
follows:
ΔV_IN
=
I_OUT
F_SW × C_IN
×
V_OUT
V_IN
× (1−
V_OUT
V_IN
)
(20)
The worst-case condition occurs at V_IN = 2V_OUT,
where:
ΔV_IN
=
1 _× I_OUT
4 F_SW × C_IN
(21)
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
ΔV_OUT
=
V_OUT
F_SW × L
× (1−
V_OUT
V_IN
)
×
(R_ESR
+
1
8 × F_SW × C_OUT
)
(22)
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
ΔV_OUT
=
V_OUT
8 × F_SW2 × L × C_OUT
× (1−
V_{OUT )}
V_IN
(23)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equation 5, 8 and 9.
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
NB6381 Rev. 1.15
www.MonolithicPower.com
14
4/18/2012
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