MPM3606GQV-P Datasheet, PDF (14/18 Pages) MPS Industries, Inc. – 21V Input, 0.6A Module Synchronous Step-Down Converter with Integrated Inductor

MPM3606 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR
and ripple degrades. So the optimal balance
point of AAM voltage for good efficiency,
stability, ripple and transient should be found
out.
Adjust the AAM threshold by connecting a
resistor from AAM pin to ground. Take Figure 6
as reference. An internal 6.2µA current source
charges the external resistor.
Figure 6: AAM Network
Generally, R4 is then given by:
V_AAM=R4 x 6.2µA
Please consult the Figure 7 below when setting
the AAM resistor.
Figure 7: AAM Resistor Selection
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low-
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
voltage ripple low. The output voltage ripple can
be estimated as:
V_OUT

V_OUT
f_S  L₁
 ^1

V_OUT
V_IN





R_ESR


1
8

f_S

C2


Where L₁ is the inductor value and R_ESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated as:
ΔV_OUT

8

V_OUT
f_S2  L₁

C2




1

V_OUT
V_IN



For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated as:
ΔV_OUT

V_OUT
f_S  L₁
 ^{}1
V_OUT
VIN



R_ESR
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MPM3606 can be optimized for a wide range of
capacitance and ESR values.
PC Board Layout ⁽¹⁰⁾
PCB layout is very important to achieve stable
operation especially for input capacitor
placement. For best results, follow these
guidelines:
1. Use large ground plane directly connect to
PGND pin. Add vias near the PGND pin if
bottom layer is ground plane.
2. The high current paths at GND, IN. Place
the ceramic input capacitor close to IN and
PGND pins. Keep the connection of input
capacitor and IN pin as short and wide as
possible.
3. The external feedback resistors should be
placed next to the FB pin.
4. Keep the feedback network away from the
switching node.
Notes:
10) The recommended layout is based on the Figure 8 Typical
Application circuit on page 16.
MPM3606 Rev. 1.0
www.MonolithicPower.com
14
8/11/2014
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