68HC05L5 Datasheet, PDF (98/200 Pages) Motorola, Inc – General Release Specification

Freescale Semiconductor, Inc.
Oscillators/Clock Distributions
7.6.6 Timebase Control Register 2
Address: $0011
Bit 7
6
5
4
3
2
1
Read: TBIF
0
0
TBIE TBR1 TBR0
0
Write:
RTBIF
COPE
Reset: 0
0
1
1
0
0
0
= Unimplemented
Figure 7-6. Timebase Control Register 2 (TBCR2)
Bit 0
0
COPC
0
Read
Anytime; bits 3 and 0 are write-only bits and always read as logic 0
Write
Anytime; bit 7 is a read-only bit and write has no effect; bit 1 is 1-time
write bit
TBIF — Timebase Interrupt Flag
The TBIF bit is set every timeout interval of the timebase counter. This
read-only bit is cleared by writing a logic 1 to the RTBIF bit. Reset
clears the TBIF bit. The timebase interrupt period between reset and
the first TBIF depends on the time elapsed during reset, since the
timebase divider is not initialized on reset.
TBIE — Timebase Interrupt Enable
The TBIE bit enables the timebase interrupt capability. If TBIF = 1 and
TBIE = 1, the timebase interrupt is generated.
0 = Timebase interrupt disabled
1 = Timebase interrupt requested when TBIF = 1
TBR1 and TBR0 — Timebase Interrupt Rate Select
The TBR1 and TBR0 bits select one of four rates for the timebase
interrupt period (see Table 7-3). The TBI rate is also related to the
COP timeout reset period. These bits are set to logic 1 on reset.
General Release Specification
MC68HC(7)05L5 — Rev. 2.0
98
Oscillators/Clock Distributions
MOTOROLA
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