68HC705V12 Datasheet, PDF (85/248 Pages) Motorola, Inc – The Motorola microcontroller

Parallel Input/Output (I/O)
Port C
data register will return the logic state of the corresponding I/O pin. The
port C data register is unaffected by reset.
7.5.2 Port C Data Direction Register
Each port C I/O pin may be programmed as an input by clearing the
corresponding bit in the port C data direction register (DDRC) or
programmed as an output by setting the corresponding bit in the DDRC.
The DDRC can be accessed at address $0006 and is cleared by reset.
7.5.3 Port C I/O Pin Interrupts
The inputs of all eight bits of port C are ANDed into the IRQ input of the
CPU. See Figure 4-2. IRQ Function Block Diagram. This port has its
own interrupt request latch to enable the user to differentiate between
the IRQ sources. The port IRQ inputs are falling edge sensitive only. Any
port C pin can be disabled as an interrupt input by setting the
corresponding DDR bit or data register bit. To enable port pin interrupts,
the corresponding DDR and data register bits must both be cleared. Any
port C pin that is configured as an output will not cause a port interrupt
when the pin transitions from a 1 to a 0.
NOTE:
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself and not to the internal IRQ input to the CPU. Therefore, BIH and
BIL cannot be used to obtain the result of the logical combination of the
eight pins of port C.
CAUTION:
Exercise caution when writing to the port C data register and data
direction register due to their interaction with the IRQ subsystem as
depicted in Figure 4-2. IRQ Function Block Diagram. Special care
should be exercised in using read/modify/write instructions on these
registers.
MC68HC705V12 — Rev. 3.0
MOTOROLA
Parallel Input/Output (I/O)
Advance Information
85