MC145506 Datasheet, PDF (8/24 Pages) Motorola, Inc – PCM CODEC FILTER MONO CIRCUIT

Freescale Semiconductor, Inc.
CCI
Convert Clock Input
CCI is designed to accept five discrete clock frequencies.
These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
2.56 MHz. The frequency at this input is compared with MSI
and prescale divided to produce the internal sequencing
clock at 128 kHz (or 16 times the sampling rate). The duty
cycle of CCI is dictated by the minimum pulse width except for
128 kHz, which is used directly for internal sequencing and
must have a 40% to 60% duty cycle. In asynchronous appli-
cations, CCI should be derived from transmit timing. (CCI is
tied internally to TDC in the MC145507.)
TDC
Transmit Data Clock Input
TDC can be any frequency from 64 kHz to 4.096 MHz, and
is often tied to CCI if the data rate is equal to one of the five
discrete frequencies. This clock is the shift clock for the trans-
mit shift register and its rising edges produce successive data
bits at TDD. TDE should be derived from this clock. (TDC and
RDC are tied together internally in the MC145508 and are
called DC.)
TDE
Transmit Data Enable Input
TDE serves three major functions. The first TDE rising
edge following an MSI rising edge, generates the internal
transmit strobe which initiates an A/D conversion. The inter-
nal transmit strobe also transfers a new PCM data word into
the transmit shift register (sign bit first) ready to be output at
TDD. The TDE pin is the high–impedance control for the
transmit digital data (TDD) output. As long as this pin is high,
the TDD output stays low impedance. This pin also enables
the output shift register for clocking out the 8–bit serial PCM
word. The logical AND of the TDE pin with the TDC pin,
clocks out a new data bit at TDD. TDE should be held high for
eight consecutive TDC cycles to clock out a complete PCM
word for byte interleaved applications. The transmit shift reg-
ister feeds back on itself to allow multiple reads of the transmit
data. If the PCM word is clocked out once per frame in a byte
interleaved system, the MSI pin function is transparent and
may be connected to TDE.
The TDE pin may be cycled during a PCM word for bit inter-
leaved applications. TDE controls both the high–impedance
state of the TDD output and the internal shift clock. TDE must
fall before TDC rises (tsu8) to ensure integrity of the next data
bit. There must be at least two TDC falling edges between the
last TDE rising edge of one frame and the first TDE rising
edge of the next frame. MSI must be available separate from
TDE for bit interleaved applications.
TDD
Transmit Digital Data Output
The output levels at this pin are controlled by the VLS pin.
For VLS connected to VDD, the output levels are from VSS
to VDD. For a voltage of VLS between VDD – 4 V and VSS, the
output levels are HCMOS compatible with VLS being the
digital ground supply and VDD being the positive logic supply.
The TDD pin is a three–state output controlled by the TDE
pin. The timing of this pin is controlled by TDC and TDE. The
data format (Mu–Law, A–Law, or sign magnitude) is con-
trolled by the Mu/A pin.
RDC
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz. This
pin is often tied to the TDC pin for applications that can use a
common clock for both transmit and receive data transfers.
The receive shift register is controlled by the receive clock
enable (RCE) pin to clock data into the receive digital data
(RDD) pin on falling RDC edges. These three signals can be
asynchronous with all other digital pins. The RDC input is in-
ternally tied to the TDC input on the MC145508 and called
DC.
RCE
Receive Clock Enable Input
The rising edge of RCE should identify the sign bit of a
receive PCM word on RDD. The next falling edge of RDC,
after a rising RCE, loads the first bit of the PCM word into the
receive register. The next seven falling edges enter the
remainder of the PCM word. On the ninth rising edge, the
receive PCM word is transferred to the receive buffer register
and the A/D sequence is interrupted to commence the
decode process. In asynchronous applications with an 8 kHz
transmit sample rate, the receive sample rate should be be-
tween 7.5 kHz and 8.5 kHz. Two receive PCM words may be
decoded and analog summed each transmit frame to allow
on–chip conferencing. The two PCM words should be
clocked in as two single PCM words, a minimum of 31.25 µs
apart, with a receive data clock of 512 kHz or faster.
RDD
Receive Digital Data Input
RDD is the receive digital data input. The timing for this pin
is controlled by RDC and RCE. The data format is determined
by the Mu/A pin.
Mu/A
Mu/A Select
This pin selects the companding law and the data format at
TDD and RDD.
Mu/A = VDD; Mu–255 Companding D3 Data Format with
Zero Code Suppress
Mu/A = VAG; Mu–255 Companding with Sign Magnitude
Data Format
Mu/A = VSS; A–Law Companding with CCITT Data Format
Bit Inversions
Code
+ Full Scale
+ Zero
– Zero
– Full Scale
Sign/
Magnitude
1111
1000
0000
0111
1111
0000
0000
1111
Mu–Law
1000
1111
0111
0000
0000
1111
1111
0010
A–Law
(CCITT)
1010
1101
0101
0010
1010
0101
0101
1010
SIGN
BIT
CHORD BITS
STEP BITS
0 1 2 3 4 5 67
NOTE: Starting from sign magnitude, to change format:
To Mu–Law —
MSB is unchanged (sign)
Invert remaining 7 bits
If code is 0000 0000, change to 0000 0010 (for zero
code suppression)
MC145506•MC145507•MC14550_F8_{or More Information On This Product,}
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