68HC05CL48 Datasheet, PDF (73/145 Pages) Motorola, Inc – SPECIFICATION (General Release)

June 11, 1997 GENERAL RELEASE SPECIFICATION
SECTION 9
SERIAL PERIPHERAL INTERFACE
The term “serial peripheral” refers to the fact that this interface requires separate
wires (signals) for data and clock. In this format, data does not contain an explicit
clock. The SPI scheme may be used to interconnect microcomputers located at a
short distance (usually within a single “black box” or on the same PC card). This
may comprise a system of one microcomputer and several slaves or may be a
system of microcomputers, each having the capability of either master or slave.
A practical system may include:
1) MISO master in slave out
2) MOSI master out slave in
3) SCK serial clock
4) SS (n) slave select(s)
9.1 SIGNAL DESCRIPTION
9.1.1 MISO Master In Slave Out
9.1.1.1 Slave Mode
MISO is the signal which is used in Slave Mode to present data from a Slave
device to the bus. The MISO pin will be placed in the hi-Z state whenever a Slave
device is “not” selected (SS=1) by the bus master. Figure 9-1 shows the clock
(SCK) and data relationship. Four possible timing relationships may be chosen by
use of the control bits (CPOL) and (CPHA). The Slave device and a Master device
must be programmed to be in similar timing modes for proper data transfer.
9.1.1.2 Master Mode
In the master mode (control bit MSTR=1), the function of MOSI and MISO are
inverted within the device. Therefore, the MISO pin becomes the data input pin for
a device which is in the master mode. (Also, the function of SCK switches from
being an input for system clock to one of outputting the system clock.)
MC68HC05CL48
REV 2.0
SERIAL PERIPHERAL INTERFACE
MOTOROLA
9-1