MC3425 Datasheet, PDF (7/12 Pages) ON Semiconductor – POWER SUPPLY SUPERVISORY/ OVER AND UNDERVOLTAGE PROTECTION CIRCUIT

MC3425
CROWBAR SCR CONSIDERATIONS
Referring to Figure 16, it can be seen that the crowbar
SCR, when activated, is subject to a large current surge from
the output capacitance, Cout. This capacitance consists of
the power supply output capacitors, the load’s decoupling
capacitors, and in the case of Figure 16A, the supply’s input
filter capacitors. This surge current is illustrated in Figure 17,
and can cause SCR failure or degradation by any one of
three mechanisms: di/dt, absolute peak surge, or I2t. The
interrelationship of these failure methods and the breadth of
the applications make specification of the SCR by the
semiconductor manufacturer difficult and expensive.
Therefore, the designer must empirically determine the SCR
and circuit elements which result in reliable and effective OVP
operation. However, an understanding of the factors which
influence the SCR’s di/dt and surge capabilities simplifies
this task.
1. di/dt
As the gate region of the SCR is driven on, its area of
conduction takes a finite amount of time to grow, starting as a
very small region and gradually spreading. Since the anode
current flows through this turned–on gate region, very high
current densities can occur in the gate region if high anode
currents appear quickly (di/dt). This can result in immediate
destruction of the SCR or gradual degradation of its forward
blocking voltage capabilities – depending on the severity of
the occasion.
The value of di/dt that an SCR can safely handle is
influenced by its construction and the characteristics of the
gate drive signal. A center–gate–fire SCR has more di/dt
capability than a corner–gate–fire type, and heavily
overdriving ( 3 to 5 times IGT) the SCR gate with a fast < 1.0
µs rise time signal will maximize its di/dt capability. A typical
maximum number in phase control SCRs of less than 50
A(RMS) rating might be 200 A/µs, assuming a gate current of
five times IGT and < 1.0 µs rise time. If having done this, a di/dt
problem is seen to still exist, the designer can also decrease
the di/dt of the current waveform by adding inductance in
series with the SCR, as shown in Figure 18. Of course, this
reduces the circuit’s ability to rapidly reduce the dc bus
voltage and a tradeoff must be made between speedy
voltage reduction and di/dt.
Figure 16. Typical Crowbar Circuit Configurations
(A) SCR Across Input of Regulator
Series
Vin
Regulator
Vout
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+
+
Cin
Cout
(B) SCR Across Output of Regulator
Vin
Series
*
Regulator
Vout
+
+
Cin
Cout
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*Needed if supply is not current limited.
MOTOROLA ANALOG IC DEVICE DATA
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