MC145483 Datasheet, PDF (7/19 Pages) Motorola, Inc – 3V 13-BIT LINEAR PCM CODEC-FILTER

FST (FSR)
BCLKT (BCLKR)
DT
1 2 3 4 5 6 7 8 9 10 11 12 13
DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13
DON’T CARE
Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)
FST (FSR)
BCLKT (BCLKR)
DT
1 2 3 4 5 6 7 8 9 10 11 12 13
DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13
DON’T CARE
Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)
FST (FSR)
SHORT OR
LONG FRAME
SYNC
BCLKT
DT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE
Figure 2c. Sign–Extended (BCLKR = 0)
Transmit and receive both use BCLKT, and the first four data bits are the sign bit.
FST may occur at a different time than FSR.
FST (FSR)
SHORT OR
LONG FRAME
SYNC
BCLKT
DT
1 2 3 4 5 6 7 8 9 10 11 12 13
DR ^{DON’T CARE} 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE
Figure 2d. Receive Gain Adjust (BCLKR = 1)
Transmit and receive both use BCLKT. FST may occur at a different time than FSR.
Bits 14, 15, and 16, clocked into DR, are used for attenuation control for the receive analog output.
MOTOROLA
Figure 2. Digital Timing Modes for the PCM Data Interface
MC145483
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