MC14034B Datasheet, PDF (7/9 Pages) Motorola, Inc – 8-Bit Universal Bus Register

SHIFT LEFT OUTPUT
A ENABLE
SHIFT LEFT/
SHIFT RIGHT
SHIFT RIGHT
INPUT
CLOCK
A/S PARALLEL
ENTRY
A1
A8
AE
REGISTER 1
P/S
MC14034B
DS
A/B
A/S
C _B1
B8
A1
A8
AE
P/S
DS
REGISTER 3
A/B
MC14034B
A/S
C _B1
B8
A1
AE
P/S
DS
A/B
A/S
CB1
A1
AE
P/S
DS
REGISTER 4
A/B
MC14034B
A/S
C _B1
AE
P/S
SHIFT RIGHT
OUTPUT
A8
REGISTER 2
MC14034B
B8
SHIFT LEFT
INPUT*
A/S
COCK
AE
A8
B8
VDD
VDD
A “High” (“Low”) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register
on the positive transition of the lock signal. A “high” on the “A” Enable Input disables the “A” parallel data lines on Reg. 1 and 2
and enables the “A” data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be
used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used, Reg. 3 and 4 and associated logic are not required.
*Shift left input must be disabled during parallel entry.
Figure 6. Shift Right/Shift Left with Parallel Inputs
MOTOROLA CMOS LOGIC DATA
MC14034B
141