MPC990 Datasheet, PDF (6/9 Pages) Motorola, Inc – LOW VOLTAGE PLL CLOCK DRIVER

MPC990 MPC991
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
tr, tf
TCLK Input Rise/Falls
3.0
ns
fref
Reference Input Frequency
Note 6.
Note 6.
MHz
frefDC
Reference Input Duty Cycle
25
75
%
6. Maximum and minimum input reference frequencies are limited by the VCO lock range and the feedback divider.
Condition
APPLICATIONS INFORMATION
Using the On–Board Crystal Oscillator
The MPC990 features an on–board crystal oscillator to
allow for seed clock generation as well as final distribution.
The on–board oscillator is completely self contained so that
the only external component required is the crystal. As the
oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the MPC990
as possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required.
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most of the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC990 with just a
minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm
lower than the specified value. For most processor
implementations a few hundred ppm translates into kHz
inaccuracies, a level which does not represent a major issue.
The MPC990 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback
to the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal.
Table 1. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental at Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150pm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR) 50 to 80Ω Max
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
Power Supply Filtering
The MPC990/991 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC990/991 provides
separate power supplies for the output buffers (VCCO) and
the internal PLL (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC990/991.
Figure 4 illustrates a typical power supply filter scheme.
The MPC990/991 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6