MPC9448 Datasheet, PDF (6/12 Pages) Motorola, Inc – 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

MPC9448
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing
Diagram
CCLK or
PCLK
CLK_STOP
Q0 to Q11
Driving Transmission Lines
The MPC9448 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17Ω (V_CC=3.3V), the
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091. In most high performance clock networks,
point--to--point distribution of signals is the method of choice.
In a point--to--point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50Ω resistance to V_CC÷2.
MPC9448
OUTPUT
BUFFER
IN
17Ω
R_S = 33Ω
Z_O = 50Ω
OutA
MPC9448
OUTPUT
BUFFER
IN
17Ω
R_S = 33Ω
Z_O = 50Ω
R_S = 33Ω
Z_O = 50Ω
OutB0
OutB1
3.0
OutA
2.5
t_D = 3.8956
2.0
In
1.5
OutB
t_D = 3.9386
1.0
0.5
0
2
4
6
8
10
12
14
TIME (nS)
Figure 5. Single versus Dual Line Termination
Waveforms
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9448 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output--to--output skew
of the MPC9448. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9448 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at V_CC=3.3V.
V_L = V_S ( Z₀ ÷ (R_S+R₀ +Z₀))
Z₀ = 50Ω || 50Ω
R_S = 33Ω || 33Ω
R₀ = 17Ω
V_L = 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
MOTOROLA
6
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TIMING SOLUTIONS