MCM67A518 Datasheet, PDF (6/12 Pages) Motorola, Inc – 32K x 18 Bit Asynchronous/Latched Address Fast Static RAM

ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM67A518–10 MCM67A518–12 MCM67A518–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Times
tAVAV
10
—
12
—
15
—
ns
4
Setup Times:
Address Valid to End of Write tAVWH
9
Address Valid to E High tAVEH
9
Address Valid to W Low tAVWL
0
Address Valid to E Low tAVEL
0
Address Valid to W High tDVWH
5
Data Valid E High tDVEH
5
ns
—
10
—
13
—
—
10
—
13
—
—
0
—
0
—
—
0
—
0
—
—
6
—
7
—
—
6
—
7
—
Hold Times:
ns
W High to Address Invalid tWHAX
0
—
0
—
0
—
E High to Address Invalid tEHAX
0
—
0
—
0
—
W High to Data Invalid tWHDX
0
—
0
—
0
—
E High to Data Invalid tEHDX
0
—
0
—
0
—
Write Pulse Width:
Write Pulse Width (G Low) tWLWH
9
Write Pulse Width (G High) tWLWH
8
Write Pulse Width tWLEF
9
Enable to End of Write tELWH
9
Enable to End of Write tELEH
9
ns
—
10
—
13
—
—
9
—
12
—
—
10
—
13
—
5
—
10
—
13
—
6
—
10
—
13
—
5, 6
Output Buffer Control:
ns
W High to Output Valid tWHQV
10
—
12
—
15
—
W High to Output Active tWHQX
3
—
3
—
5
—
7
W Low to Output High–Z tWLQZ
0
5
0
6
0
9
7, 8
NOTES:
1. W (write) refers to either one or both byte write enables LW and UW.
2. AL and DL are equal to VIH for all asynchronous cycles.
3. Both Write Enables must be equal to VIH for all address transitions.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes high coincident with or before W goes high the output will remain in a high impedance state.
6. If E goes low coincident with or after W goes low the output will remain in a high impedance state.
7. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tWLQZ is less than tWHQX for a given device.
8. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
MCM67A518
6
MOTOROLA FAST SRAM