MCM6726D Datasheet, PDF (6/7 Pages) Motorola, Inc – 128K x 8 Bit Fast Static Random Access Memory

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6726D–8
6726D–10
6726D–12
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Enable to End of Write
tAVAV
tAVEL
tAVEH
tELEH,
tELWH
8
—
10
—
12
—
ns
3
0
—
0
—
0
—
ns
7
—
8
—
9
—
ns
7
—
8
—
9
—
ns
4,5
Data Valid to End of Write
tDVEH
4
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 2
tAVAV
tAVEH
tAVEL
tELEH
tELWH
tEHAX
HIGH–Z
tDVEH
DATA VALID
tEHDX
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
MCM 6726D WJ XX X
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns)
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6726DWJ8 MCM6726DWJ10
MCM6726DWJ12
MCM6726DWJ8R MCM6726DWJ10R MCM6726DWJ12R
MCM6726D
6
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