MCM72BF32 Datasheet, PDF (5/14 Pages) Motorola, Inc – 256KB and 512KB BurstRAM Secondary Cache Module for Pentium

K
ADSC
ADSP
A0 – A15
MCM67B618 BLOCK DIAGRAM (See Note)
ADV
BURST LOGIC
Q0
A0
Q1
CLR
A1
INTERNAL
ADDRESS
A0′
16
A1′
64K × 18
MEMORY
ARRAY
ADDRESS
REGISTER
2
A1 – A0
16
A2 – A15
18
99
WRITE
UW
REGISTER
LW
DATA–IN
REGISTERS
E
G
9
DQ0 – DQ8
9
DQ9 – DQ17
ENABLE
REGISTER
9
9
OUTPUT
BUFFER
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting
ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid
data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address
A15 – A2
A1
A0
1st Burst Address
A15 – A2
A1
A0
2nd Burst Address
A15 – A2
A1
A0
3rd Burst Address
A15 – A2
A1
A0
NOTE: The burst wraps around to its initial state upon completion.
MOTOROLA FAST SRAM
MCM72BF32•MCM72BF64
5