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MC88LV915T_01 Datasheet, PDF (5/12 Pages) Motorola, Inc – Low Voltage Low Skew CMOS PLL Clock Driver, 3-State | |||
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FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)
Symbol
Parameter
Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output
Fmax (âQâ)
Maximum Operating Frequency,
Q0âQ3 Outputs
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phaseâlocked condition.
Guaranteed Minimum
100
50
Unit
MHz
MHz
AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50⦠Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
tPULSE WIDTH
(Q0âQ4, Q5, Q/2)
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
Q5, Q/2 @ VCC/2
0.5
0.5tCYCLE â 0.5 1
2.0
0.5tCYCLE + 0.5 1
ns Into a 50⦠Load
Terminated to VCC/2
ns Into a 50⦠Load
Terminated to VCC/2
tPULSE WIDTH
(2X_Q Output)
Output Pulse Width:
2X_Q @ 1.5V
40MHz
66MHz
80MHz
100MHz
0.5tCYCLE â 1.5
0.5tCYCLE â 1.0
0.5tCYCLE â 1.0
0.5tCYCLE â 1.0
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
ns Into a 50⦠Load
Terminated to VCC/2
tCYCLE
(2x_Q Output)
CycleâtoâCycle Variation
2x_Q @ VCC/2
40MHz
66MHz
80MHz
100MHz
tCYCLE â 600ps
tCYCLE â 300ps
tCYCLE â 300ps
tCYCLE â 400ps
tCYCLE + 600ps
tCYCLE + 300ps
tCYCLE + 300ps
tCYCLE + 400ps
tPD2
(With 1M⦠from RC1 to An VCC)
ns
SYNC Feedback
SYNC Input to Feedback Delay 66MHz
â1.65
â1.05
(Measured at SYNC0 or 1 and 80MHz
â1.45
â0.85
FEEDBACK Input Pins)
100MHz
â1.25
â0.65
tSKEWr3
OutputâtoâOutput Skew Between Outputs
â
(Rising) See Note 4 Q0âQ4, Q/2 (Rising Edges Only)
tSKEWf3
(Falling)
OutputâtoâOutput Skew Between Outputs
â
Q0âQ4 (Falling Edges Only)
tSKEWall3
OutputâtoâOutput Skew 2X_Q, Q/2,
â
Q0âQ4 Rising, Q5 Falling
tLOCK4
Time Required to Acquire PhaseâLock
1.0
From Time SYNC Input Signal is
Received
500
ps All Outputs Into a
Matched 50⦠Load
Terminated to VCC/2
750
ps All Outputs Into a
Matched 50⦠Load
Terminated to VCC/2
750
ps All Outputs Into a
Matched 50⦠Load
Terminated to VCC/2
10
ms Also Time to LOCK
Indicator High
tPZL5
Output Enable Time OE/RST to 2X_Q,
3.0
Q0âQ4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
tPHZ,tPLZ5
Output Disable Time OE/RST to 2X_Q,
3.0
Q0âQ4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specificationâs min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully poweredâon, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with
C1 = 0.01µF.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when âMCâ status is reached.
MOTOROLA
5
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