MC44145 Datasheet, PDF (5/8 Pages) Motorola, Inc – PIXEL CLOCK GENERATOR / SYNC SEPARATOR

MC44145
CIRCUIT OPERATION
Composite Sync Separator
The sync separator is an adaptive slicer. It will output
“raw” sync data. Two outputs are given, thus allowing one
output to be used for composite sync and the other output to
be integrated and then sliced using the inverting slicing
amplifier provided. As the input of the slicing amplifier is
external, the amplifier may be driven from either sync output,
although normally the high impedance output (Sync B)
would be recommended.
The positive video input signal required is nominally 1.0 V
sync–to–white, but the circuit supports signals above and
below this level and also is resistant to a degree of reflections
on the signal. Coupling to the sync separator may be
achieved by a simple capacitor of 100 nF, but better results
may be obtained with a higher value in series with a
resistance of 1.0 kΩ.
Clock Generator
The system is best put to use in a dual loop configuration;
a first loop locks to line frequency by means of a type I phase
detector (multiplier type) which is insensitive to missing
pulses. This PLL is then followed by a second loop using the
MC44145, performing frequency multiplication. The phase
comparator of the MC44145 is frequency and phase
sensitive. It is a type IV (sequential type) phase detector,
which does not tolerate missing pulses. The dual loop
structure makes up a noise insensitive frequency (and
phase) locked loop.
The phase and frequency comparator provides two logical
outputs, mutually exclusive – up or down – that are used to
source or sink current to and from the loop filter. This current
can be user–selected to be 40 µA or 80 µA (typical), thus
providing some degree of loop gain control.
The VCO is an emitter–coupled multivibrator type, with an
on–chip timing capacitor, and has been designed for low
phase noise.
The divide–by–2 is included at the output of the VCO, thus
allowing for a precise 50% duty cycle, hence the VCO is
operating at twice the required frequency. The divider can be
bypassed, bringing the VCO output directly to the output
buffer.
The external divider must provide a feedback pulse to
close the loop; the falling edge of this pulse will be aligned
(when the loop is in lock) with the rising edge of the pulse
applied to the Fref input. Operation of the phase comparator
is insensitive to the duty cycle of both its inputs. The feedback
pulse should have a minimum width of 500 ns. This can be
guaranteed if it has a length of at least 16 output clock cycles
(highest output frequency with the divider disabled).
APPLICATION INFORMATION
Analog video signals out of the MC44011 are sampled and
converted to 8–bits digital in the A/D converter (MC44250
series) by means of the clock provided by the MC44145,
pixel clock generator (see Figure 1).
The frame store contains the memory, the necessary logic
for the memory addressing, as well as the counter to set the
frequency multiplication ratio of the line locked clock
generator (H. Count).
Figure 1. Application Block Diagram
Video
Digital
Multistandard
Decoder
MC44011
R (Y)
G (U)
B (V)
A/D
Converter
MC44250
Frame Store
R (Y)
G (U)
B (V)
Pixel Clock
Generator
MC44145
Pixel Clock
H. Count
Vertical Sync
MOTOROLA ANALOG IC DEVICE DATA
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