MC74HC7266A Datasheet, PDF (4/6 Pages) Motorola, Inc – Quad 2-Input Exclusive NOR Gate

MC74HC7266A
LOGIC DETAIL
(1/4 of Device)
A
Y
B
APPLICATION INFORMATION
Bi φ–L is defined as biphase–level code. Also known as
Manchester Code, this technique utilizes binary phase shift
keying (PSK). The Bi φ–L output shown in Figure 3 carries
both data and synchronization information; therefore, sepa-
rate data and clock lines are not required to transfer informa-
tion. A positive–going transition in the middle of the bit
interval indicates a logic zero; a negative–going transition in-
dicates a logic one (see Figure 4).
NRZ–L shown in Figure 3 is non–return–to–zero level
code. This is simply serial data out of a shift register, such as
the HC597.
The Bi φ–L signal must be phase coherent (i.e., no
glitches). Therefore, NRZ–L and clock transitions must be
coincident.
NRZ–L
CLOCK
1/4
HC7266A
BI φ–L
Figure 3. Biphase–Level Encoder (Manchester Encoder)
NRZ–L
CLOCK
BI φ–L
POSITIVE
LOGIC DATA
1
0
1
1
0
0
BIT
INTERVAL
Figure 4. Timing Diagram
MOTOROLA
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6