MC74HC03A Datasheet, PDF (4/7 Pages) ON Semiconductor – Quad 2-Input NAND Gate with Open-Drain Outputs

MC74HC03A
INPUT A
OUTPUT Y
tr
tf
90%
50%
10%
tPZL tPLZ
90%
50%
10%
10%
tTHL
Figure 1. Switching Waveforms
VCC
GND
HIGH
IMPEDANCE
VOL
VCC
DEVICE
UNDER
TEST
1kΩ
OUTPUT
Rpd
TEST
POINT
CL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
25
TYPICAL
T=25°C
20
VCC=5V
T=25°C
15
T=85°C
10
T=125°C
EXPECTED MINIMUM*
5
0
0
1
2
3
4
5
VO, OUTPUT VOLTAGE (VOLTS)
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open–Drain Output Characteristics
VCC
A1
1/4
Y1
B1
HC03
A2
1/4
Y2
B2
HC03
PULLUP
RESISTOR
OUTPUT
An
1/4
Yn
Bn
HC03
OUTPUT = Y1 • Y2 • . . . • Yn
= A1B1 • A2B2 • . . . • AnBn
Figure 4. Wired AND
LED1
LED2
LED
ENABLE
VCC
+
VR
–
+
VF
–
1/4
HC03
VCC
1/4
HC03
^ ^{DESIGN EXAMPLE}
CONDITIONS: ID 10mA
^ ^{USING FIGURE NO TAG TYPICAL}
CURVE, at ID=10mA, VDS 0.4V
N + ^{* *} R
VCC VF
ID
VO
+ ^{* * 5V 1.7V 0.4V}
10mA
+ 290W
USE R = 270Ω
Figure 5. LED Driver With Blanking
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6