MC14LC5540 Datasheet, PDF (4/18 Pages) Motorola, Inc – ADPCM Codec

high–impedance state, thus allowing the TG pin to serve as a
high–impedance input to the transmit filter.
RO
Receive Analog Output
(PDIP, SOG—Pin 5; TQFP—Pin 1)
This is the non–inverting output of the receive smoothing
filter from the digital–to–analog converter. This output is
capable of driving a 2 kΩ load to 1.575 V peak referenced to
the VAG pin. This pin may be dc referenced to either the VAG
pin or a voltage of half of VEXT by BR2 (b7). This pin is high
impedance when the device is in the analog power–down
mode. This pin is high impedance except when it is enabled
for analog signal output.
AXO–
Auxiliary Audio Power Output (Inverting)
(PDIP, SOG—Pin 6; TQFP—Pin 3)
This is the inverting output of the auxiliary power output
drivers. The Auxiliary Power Driver is capable of differentially
driving a 300 Ω load. This power amplifier is powered from
VEXT and its output can swing to within 0.5 V of VSS and
VEXT. This pin may be dc referenced to either the VAG pin or
a voltage of half of VEXT by BR2 (b7). This pin is high imped-
ance in power down. This pin is high impedance except
when it is enabled for analog signal output.
AXO+
Auxiliary Audio Power Output (Non–Inverting)
(PDIP, SOG—Pin 7; TQFP—Pin 4)
This is the non–inverting output of the auxiliary power out-
put drivers. The Auxiliary Power Driver is capable of differen-
tially driving a 300 Ω load. This power amplifier is powered
from VEXT and its output can swing to within 0.5 V of VSS and
VEXT. This pin may be dc referenced to either the VAG pin or
a voltage of half of VEXT by BR2 (b7). This pin is high imped-
ance in power down. This pin is high impedance except
when it is enabled for analog signal output.
PI
Power Amplifier Input
(PDIP, SOG—Pin 10; TQFP—Pin 8)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier may be dc referenced to
either the VAG pin or a voltage of half of VEXT by BR2 (b7).
The PI and PO– pins are used with external resistors in an
inverting op amp gain circuit to set the gain of the PO + and
PO– push–pull power amplifier outputs. Connecting PI to
VDD will power down these amplifiers and the PO+ and PO–
outputs will be high impedance.
PO–
Power Amplifier Output (Inverting)
(PDIP, SOG—Pin 11; TQFP—Pin 9)
This is the inverting power amplifier output that is used to
provide a feedback signal to the PI pin to set the gain of the
push–pull power amplifier outputs. This power amplifier is
powered from VEXT and its output can swing to within 0.5 V
of VSS and VEXT. This should be noted when setting the gain
of this amplifier. This pin is capable of driving a 300 Ω load to
PO+ independent of supply voltage. The PO+ and PO– out-
puts are differential (push–pull) and capable of driving a
300 Ω load to 3.15 V peak, which is 6.3 V peak–to–peak
when a nominal 5 V power supply is used for VEXT. The bias
voltage and signal reference for this pin may be dc refer-
enced to either the VAG pin or a voltage of half of VEXT by
BR2 (b7). Low impedance loads must be between PO+ and
PO–. This pin is high impedance when the device is in the
analog power–down mode. This pin is high impedance ex-
cept when it is enabled for analog signal output.
PO+
Power Amplifier Output (Non–Inverting)
(PDIP, SOG—Pin 12; TQFP—Pin 10)
This is the non–inverting power amplifier output that is an
inverted version of the signal at PO–. This power amplifier is
powered from VEXT and its output can swing to within 0.5 V
of VSS and VEXT. This pin is capable of driving a 300 Ω load
to PO–. This pin may be dc referenced to either the VAG pin
or a voltage of half of VEXT by BR2 (b7). This pin is high
impedance when the device is in the analog power–down
mode. See PI and PO– for more information. This pin is high
impedance except when it is enabled for analog signal out-
put.
ADPCM/PCM SERIAL INTERFACE PINS
FST
Frame Sync, Transmit
(PDIP, SOG—Pin 18; TQFP—Pin 16)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
output of the serial ADPCM data at the DT pin.
BCLKT
Bit Clock, Transmit
(PDIP, SOG—Pin 19; TQFP—Pin 17)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
5120 kHz.
DT
Data, Transmit (PDIP, SOG—Pin 20; TQFP—Pin 18)
This pin is controlled by FST and BCLKT and is high im-
pedance except when outputting data.
SPC
Signal Processor Clock
(PDIP, SOG—Pin 21; TQFP—Pin 19)
This input requires a 20.48 to 24.32 MHz clock signal that
is used as the DSP engine master clock. Internally the device
divides down this clock to generate the 256 kHz clock re-
quired by the PCM Codec. The SPC clock should be a multi-
ple of 256 kHz. (This clock may be optionally specified for
higher frequencies; contact the factory for more information.)
DR
Data, Receive (PDIP, SOG, TQFP—Pin 25)
ADPCM data to be decoded are applied to this input,
which operates synchronously with FSR and BCLKR to enter
the data in a serial format.
MC14LC5540
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MOTOROLA