MC144144 Datasheet, PDF (35/44 Pages) Motorola, Inc – Enhanced Closed-Caption Decoder CMOS

BLOCK DIAGRAM DESCRIPTION
The MC144144 is designed to process both fields of Line
21 of the television VBI and provide the functional perfor-
mance of a Line 21 closed–caption decoder and extended
data service decoder. It requires two input signals, composite
video and a horizontal timing signal (HIN), and several pas-
sive components for proper operation. A vertical input signal
is also required if OSD display mode is desired when no vid-
eo signal is present. The decoder performs several func-
tions, namely extraction of the data from Line 21, separation
of the normal Line 21 data from the XDS data, display of the
selected data, and outputting of the XDS data.
The block diagram is shown at the beginning of this data
sheet.
INPUT SIGNALS
The composite video input should be a signal which is
nominally 1.0 Vp–p with sync tips negative and band limited
to 600 kHz. The MC144144 will operate with an input level
variation of at least ± 3 dB.
The HIN input signal is required to bring the VCO close to
the desired operating frequency. It must be a CMOS level
signal. The HIN signal can have positive or negative polarity
and is only required to be within 3% of the standard H fre-
quency. When configured for EXT HLK operation, this signal
should correspond to the H flyback signal.
The timing difference between HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors which will effect the horizontal position of the dis-
play. Any shift resulting from the timing of this signal can be
compensated for with the horizontal timing value in the H
position register.
VIDEO INPUT SIGNAL PROCESSING
The comp video input is ac coupled to the IC where the
sync tip is internally clamped to a fixed reference voltage by
means of a dual clamp. Initially, the unlocked signal is
clamped using a simple clamp. Improved impulse noise per-
formance is then achieved after the internal sync circuits lock
to the incoming signal. Noise rejection is obtained by making
the clamp operative only during the sync tip. The clamped
composite video signal is fed to both the data slicer and sync
slicer blocks.
The data slicer generates a clean CMOS level data signal
by slicing the signal at its midpoint. The slice level is estab-
lished on an adaptive basis during Line 21. The resultant val-
ue is stored until the next occurrence of that Line 21. A high
level of noise immunity is achieved by using this process.
The sync slicer processes the clamped comp video signal
to extract comp sync. This signal is used to lock the internally
generated sync to the incoming video when the video lock
mode of operation has been enabled. Sync slicing is per-
formed in two steps. In the non–locked mode, the sync is
sliced at a fixed offset level from the sync tip. When proper
lock operation has been achieved, the slice level voltage
switches from a fixed reference level to an adaptive level.
The slice level is stored on the sync slice capacitor, CSYNC.
The data clock recovery circuit operates in conjunction
with the digital H lock circuit. They produce a 32 H clock sig-
nal (DCLK) that is locked in phase to the clock run–in burst
portion of the sliced data obtained from the data slicer. When
Line 21 code appears, DCLK phase lock is achieved during
MOTOROLA
the clock run–in burst and used to reclock the sliced data.
Once phase lock is established it is maintained until a
change in video signal occurs.
The digital H lock circuit produces the video timing gates,
PG, STG, etc., which are locked in phase with HSYNC, the
video timing signal, no matter which H lock mode is used in
the display generation circuits. This independent phase lock
loop is able to respond quickly to changes in video timing,
without concern for display stability requirements.
VCO AND ONE SHOT
All internal timing and synchronizing signals are derived
from the on–board 12 MHz VCO. Its output is the dot Clk sig-
nal used to drive the horizontal and vertical counter chains
and for display timing. The one shot circuit produces a hori-
zontal timing signal derived from the incoming video and
qualified by the copy guard logic circuits.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display tim-
ing signal is available, the VCO is locked to the HIN input
through the action of the phase detector (PH2). When a
proper HIN signal is not available, such as in a VCR, the
VCO can be locked to the incoming video through the phase
detector (PH1). In this case the frequency detector (FR) cir-
cuit is activated as required to bring the VCO within the pull–
in range of PH1.
TIMING AND COUNTING CIRCUITS
The dot Clk is first divided down to produce the character
timing clock CHAR CLK. This signal is then further divided to
generate the horizontal timing signals: H, 2H, and HSQR.
These timing signals are used in the data output (display) cir-
cuits.
The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock and to time the display and control functions required for
proper operation. The H signal is also used to generate the
smooth scroll timing signal for display.
The V lock circuits produce a noise–free vertical pulse
derived from the horizontal timing signal. When user selects
video as the vertical lock source, the internal synchronizing
signals are phased up with the incoming video by comparing
the internally generated vertical pulse to an input vertical
pulse derived from the comp sync signal provided by the
sync slicer. In the vertical lock set to VIN mode the VIN signal
is used in place of the signal derived from comp sync. In
either case, when proper phasing has been established, this
circuit outputs the LOCK signal which is used to provide
additional noise immunity to the slicing circuits.
The LOCKed state is established only after several
successive fields have occurred in which these two vertical
pulses remain in sync. Once LOCKed, the internal timing will
flywheel until such time as the two vertical pulses lose coinci-
dence for a number of consecutive fields. Until LOCK is es-
tablished, the decoder operates on a pulse for pulse basis.
COMMAND PROCESSOR
The command processor circuit controls the manipulation
of the data for storage and display. It processes the control
port input commands to determine the display status desired
and the data channel selected. During the display time (lines
43 – 237), this information is used to control the loading, ad-
dressing and clearing of the display RAM and the operations
of the character ROM and output logic circuits.
MC144144
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