MC44722 Datasheet, PDF (33/35 Pages) Motorola, Inc – NTSC Digital Video Encoder

device-address 42, 43(hex) or 1C, 1D(hex)
ChipA
DVdd
DVdd
DVss
DVss
DVIN
TP0~7
TVIN
clock
Reset
PAL/NTSC
$71-4
$71-5 $71-6
Sync_gen
$71-2,1,0 : H_
phase
$7A-7,6,5,4,3,2,1B,0G
$71-7
copy
protection
VID_gen
$80~82
$87-3
CC_gen
$83~86
$87-1,0
$76-5
H,V _Y
demux
Cb
Cr
0
off_set
$76-7
$73-4
0
Modulator
0
$74~77
$71-7 : non_inter/interlaced
$72-3 : 625line/525line
$76-6 ^$73-5
subcarrier
gen
0
$73-6
bus
$72-1,0
I2C / SPI
TEST
bus
0
$76-3
0
$76-5
0
$76-4
MC44722/3
YVdd
CVBSVdd
CVdd
YOUT
YOUT
CVBS/CbOUT
CVBS/CbOUT
C/CrOUT
C/CrOUT
VReff
Ibias
DAVdd
DAVss
%% I2C-BUS Slave Receiver Sub-address map %%
70h:[7]
burst control (default 0:on)
[6]
self counter reset switch (default 0:off)
[5]
color bar select (defalut 0:Luma 100% Chroma 100%)
[4]
vertical blanking switch(default 0:off)
[3]
EXT pin output mode select (Csync:1, Flame sync:0)
[2]
F/Vsync select(default 0:Vsync)
[1:0]
Master/Slave mode select(default 01:656_slave)
71h:[7]
interlaced / non-interlaced
(default 0:interlaced)
[6]
VBI input control on EXT pin (default 0:off)
[5]
horizontal sync polarity (default 0)
[4]
vertical sync polarity (default 0)
[3]
flame sync polarity (default 0)
[2:0]
hsync delay control (default 100:0 clock delay)
(In slave mode can use with 7A[7:0])
72h:[7]
sub-currier phase syncronaiation(default 0)
[6]
Test mode (default 0:off)
[5]
EXT I/O switch(defalt 1:cysnc output)
[4]
color bar generate(default 0:off)
[3]
setup level control(default 1:7.5IRE)
[2]
625lines50Hz/525Lines60Hz
(default set PAL/NTSC pin)
[1:0]
PAL/NTSC (default set PAL/NTSC pin)
77h[7:0]
78h[7:0]
79h[1:0]
79h:[7:2]
7A[7:0]
7B[7:6]
7B[5:4]
7B[3:2]
7B[1]
7B[0]
80~82h:
83h[7:0]
84h[7:0]
85h[7:0]
86h[7:0]
87h[7:3]
[2]
[1]
[0]
n.a
sub-currier phase control(default 00h)
sub-currier phase control(default 00)
n.a.
hsync-delay control
(In slave mode, is valid with 71h[2:] register)
n.a
Cr clock timing delay in 16-bit digital input mode
Cb clock timing delay in 16-bit digital input mode
Y clock timing delay in 16-bit digital input mode
16-bit multiplexed CbYCrY digital input mode
(default 0: 8-bit multiplexed CbYCrY mode)
Video ID characters for field1(line20)/field2(line283)
CC character1(line21) (default 'h80)
CC character2(line21) (default 'h80)
CC character1(line284) (default 'h80)
CC character2(line284) (default 'h80)
n.a.
CGMS on/off (default 0: off)
CC closed caption/extended data for field2 encoding
(default 0: off)
CC closed caption/extended data for field1 encoding
(default 0: off)
73h[7:0]
00:NTSC/M
01:PAL/BGHL
(10:PAL/M) (11:PAL/N)
Y_register(default 80h)
<<<<<<<< M-BUS Format >>>>>>
** WRITE MODE **
S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P
74h[7:0]
75h[7:0]
76h[7]
[6]
[5]
[4]
[3]
U_register(default 79d:ntsc/157d:PAL)
V_register(default 128d:ntsc/107d:PAL)
Cr on/off (default 0:on)
Cb on/off (default 0:on)
Luma on/off(default 0:on)
(default 0: on)
CVBS/Cb DAC on/off(default 0: on)
C/Cr DAC on/off(default 0: on)
S
Slave_address
A
Sub_address
Data0
DataN
P
Start condition
42(hex) or 1C(hex)
Acknowledge generated by me
Sub_address register
First data
Continued data(address is auto incremented)
Stop condition
[2]
C/Cr DAC on/off(default 0: on)
[1]
CBVS/Y/C Y/Cr/Cb output control swith
<<<<<<<< SPI-Bus Format >>>>>>
(default 0 : CBVS/Y/C output)
** WRITE MODE **
[0]
reserved
S | Write Command | Sub_address | Data0 | ... | DataN | P
S
Write Command
Sub_address
Data0
DataN
Chip select on (High to Low)
42(hex) or 1C(hex)
Sub_address byte
First data
Continued data byte(address is auto incremented)
P
No. 33
Chip select off (Low to High)
MC44722/3 Rev 0.23 3/24/'97
This document contains information on a new product. Specifications and information herein are subject to change without notice.