MCM64Z836 Datasheet, PDF (31/34 Pages) Motorola, Inc – 256K x 36 and 512K x 18 Bit ZBT Fast Static RAM

Freescale Semiconductor, Inc.
STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
IDCODE
001** Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
HIGH–Z
010
Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins
to High–Z. NOT IEEE 1149.1 COMPLIANT.
BYPASS
011
Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1
COMPLIANT.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT.
* Instruction codes expressed in binary, MSB on left, LSB on right.
** Default instruction automatically loaded when TRST asserted or in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
000
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
NO OP
111
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
TEST–LOGIC
1
RESET
0
RUN–TEST/
1
0
IDLE
SELECT
DR–SCAN
1
0
1
CAPTURE–DR
0
SHIFT–DR
0
1
1
EXIT1–DR
0
PAUSE–DR
0
1
0
EXIT2–DR
1
UPDATE–DR
1
0
SELECT
IR–SCAN
1
0
1
CAPTURE–IR
0
SHIFT–IR
0
1
1
EXIT1–IR
0
PAUSE–IR
0
1
0
EXIT2–IR
1
UPDATE–IR
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 13. TAP Controller State Diagram
MOTOROLA FAST SRAM
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MCM64Z836•MCM64Z918
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