MC44724A Datasheet, PDF (31/45 Pages) Motorola, Inc – Advanced Digital Video Encoder

Freescale Semiconductor, Inc.
Sub-address 71 : Sync control (write/read)
MSB
LSB
Register 71 non-inter VBI SW h-polarity v-polarity f-polarity h- delay2 h-delay1 h-delay0
default : 0000_0100(bin)
non-inter
VBI SW
h-polarity
v-polarity
f-polarity
h-delay2
h-delay1
h-delay0
: non-interlaced mode select
0 : interlace mode (default)
1 : non-interlace mode
: vertical blanking information signal input control switch on 48 pin
0 : VBI input Off (default)
1 : VBI input On
: polarity of Hsync
0 : negative (default)
1 : positive
: polarity of Vsync
0 : negative (default)
1 : positive
: polarity of Fsync
0 : field1 (odd) = low level (default)
1 : field1 (odd) = high level
: delay on Hsync with reference to DVIA/DVIB data in Master mode
000: + 4 clock delay
001: + 3 clock delay
010: + 2 clock delay
011: + 1 clock delay
100: + 0 clock delay
101: - 1 clock delay
110: - 2 clock delay
111: - 3 clock delay
Note : this h-delay can be also related with 7A[7:0] register and can
delay totally +2023 clock delay in H/V or H/Fsync slave mode.
This
document
contains
For
information
More Inf^No^or^.m³¹ation On This Product,
on a new^Gp^orod^tuc^ot.^:Sp^weci^wfica^wtion^.s^fran^ed^einf^sor^cm^aati^lo^en h^.e^cre^oin^mare subject to
MC44724A/5A
change without notice.
Rev 0.05 07/15/98