C3ENPA1-DS Datasheet, PDF (31/114 Pages) Motorola, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
31
Clock Signals Table 6 describes the C-3e NP clock signals.
Table 6 Clock and Reference Signals
SIGNAL NAME PIN #
TOTAL TYPE
I/O SIGNAL DESCRIPTION
SCLK*
SCLKX*
F14
1
F15
1
LVPECL I
LVPECL I
Core Clock Rate (Differential)
CCLK0
CCLK1
CCLK2
CCLK3
CPREF†
TOTAL
F16
1
E16
1
E15
1
E14
1
D16
1
7
LVTTL I_PD Programmable CP Clock Input
LVTTL I_PD Programmable CP Clock Input
LVTTL I_PD Programmable CP Clock Input
LVTTL I_PD Programmable CP Clock Input
LVPECL I_PD Reference
* _{SCLK and SCLKX must not be AC-coupled.}
† _{If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must}
be wired to an external reference, as specified in Table 34 on page 73. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected.
CP Interface Signals
The C-3e NP’s 8 external CPs support various network physical interfaces, providing a
serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register
set. Many interfaces are possible by programming the configuration registers. CPs can be
used individually or in a cluster (four CPs) to implement the various interfaces.
Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP. All pins are capable of receiving data, with some
configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can
be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally
configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for
receive and four for transmit) or four CPs that share the transmit and receive functions for
non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03