MVME147 Datasheet, PDF (3/4 Pages) Motorola, Inc – Single-board computer

MVME6000
VMEbus
Interface
EPROM
4 Sockets
2 Banks
LXT901
Serial
Interface
Adapter
AM7990
Ethernet
Transceiver
33C93
SCSI
Interface
Adapter
8530
Serial
Controller
(two)
PCC
ASIC
Centronics
Printer
Interface
MC68030
MPU
MC68882
FPC
GCC
ASIC
4 to 32MB
DRAM Memory
Array with Parity
M48T18
Battery-Backed
4KB NVRAM/Clock
MVME147 Block Diagram
Performance
16 MHz
25 MHz
33.33 MHz
Access Sequence
MPU to Local DRAM
No Parity
Delayed Parity
Parity
MPU to Local ROM
VMEbus to Local DRAM
MPU to Global RAM
VMEbus Master
System Controller/Not Master
Not System Controller/Not Master
Read Cycles Write Cycles Read Cycles Write Cycles Read Cycles Write Cycles
4
N/A
N/A
9
13
813ns
4
N/A
N/A
9
11
688ns
4
4
5
13
13
520ns
4
4
4
13
11
440ns
4
4
5
16
13
390ns
4
4
4
16
11
330ns
6+A
11 + B
9+C
6+A
11 + B
9+C
9+A
17 + B
15 + C
9+A
17 + B
15 + C
12 + A
22 + B
19 + C
12 + A
22 + B
19 + C
Notes:
1. No arbitration overhead.
2. Except RMW cycles where the MVME147 is required to obtain VMEbus mastership before RMW cycle can be started.
3. Device access time must be 200ns or less.
4. DS0*/DS1* asserted to DTACK* asserted.
5. Typical values. Actual values may be greater or less depending on the state of the slave device.
6. A = ta/T cycles.
7. B = (ta + tr)/T cycles.
8. C = (ta + tg)/T cycles.
ta = DS0*/DS1* to the assertion of DTACK* (slave access time).
tr = Brx* low to BBSY high and AS* high (bus requested and granted).
tg = Brx* low to BGINx* low and AS* high (bus requested and granted).
T = MPU clock period, 16 MHz = 62.5 ns, 25 MHz = 40 ns, 33.33 MHz = 30 ns.
Notes
1, 2
1, 2
1, 2
1, 3
4, 5
5, 6
5, 7
5, 8