MCF5206 Datasheet, PDF (3/8 Pages) Motorola, Inc – MCF5206 Integrated Microprocessor

Freescale Semiconductor, Inc.
OVERVIEW
Figure 1 is a block diagram of the MCF5206 processor. The paragraphs that follow provide an overview of the
integrated processor.
CLOCK
INPUT
JTAG
INTERFACE
CLOCK
JTAG
512 BYTE ICACHE
512 BYTE SRAM
DRAM
CONTROLLER
CHIP
SELECTS
INTERRUPT
CONTROLLER
EXTERNAL
BUS INTERFACE
PARALLEL
PORT
DRAM
CONTROL
CHIP
SELECTS
INTERRUPT
SUPPORT
EXTERNAL
BUS
PARALLEL
INTERFACE
DUART
SERIAL
INTERFACE
BDM
INTERFACE
COLDFIRE
CORE
TIMERS
M-BUS
MODULE
TIMER
SUPPORT
M-BUS
INTERFACE
Figure 1. MCF5206 Block Diagram
ColdFire Processor Core
The ColdFire processor core consists of two independent, decoupled pipeline structures to maximize
performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage pipeline for
prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution
pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required
function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO
queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing time
stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC
datapath with a dual-read-ported register file feeding an arithmetic/logic unit.
Instruction Cache
The instruction cache improves system performance by providing cached instructions to the execution unit in
a single clock. The MCF5206 processor uses a 512-byte, direct-mapped instruction cache to achieve 17 MIPS
at 33 Mhz.The cache is accessed by physical addresses, where each 16-byte line consists of an address tag
and a valid bit.
The instruction cache also includes a bursting interface for 32-, 16-, and 8-bit port sizes to quickly fill cache
lines.
MOTOROLA
MCF5206 PRODUCT INFORMATION
3
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