MC74VHC00 Datasheet, PDF (3/5 Pages) Motorola, Inc – Quad 2-Input NAND Gate

MC74VHC00
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC ELECTRICAL CHARACTERISTICS}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ICC
Parameter
Input Leakage Current
Quiescent Supply
Current
Test Conditions
Vin = 5.5V or GND
Vin = VCC or GND
VCC
V
0 to 5.5
5.5
TA = 25°C
Min
Typ
Max
± 0.1
2.0
TA = – 40 to 85°C
Min
Max Unit
± 1.0
µA
20.0
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Parameter
Propagation Delay,
A or B to Y
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Input Capacitance
Test Conditions
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
TA = 25°C
Min
Typ
Max
5.5
7.9
8.0
11.4
3.7
5.5
5.2
7.5
4
10
TA = – 40 to 85°C
Min
Max Unit
1.0
9.5
ns
1.0
13.0
1.0
6.5
1.0
8.5
10
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 1.)
19
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Averageoperating current can be obtained by the equation: ICC(OPR₎ = CPD  VCC  fin + ICC / 4 (per gate). CPD is used to determine the no–load
dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
VIHD
Quiet Output Minimum Dynamic VOL
Minimum High Level Dynamic Input Voltage
– 0.3
– 0.8
V
3.5
V
VILD Maximum Low Level Dynamic Input Voltage
1.5
V
A or B
50%
Y
tPLH
50% VCC
VCC
GND
tPHL
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
INPUT
Figure 3. Input Equivalent Circuit
VHC Data – Advanced CMOS Logic
3
DL203 — Rev 1
MOTOROLA