DSP56F801 Datasheet, PDF (3/40 Pages) Motorola, Inc – 16-bit Digital Signal Processor

DSP56F801 Description
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
• Eleven multiplexed General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) watchdog timer
• One dedicated external interrupt pin
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
• Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator
for lower system cost and two additional GPIO lines
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 DSP56F801 Description
The DSP56F801 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F801 is well-suited for many applications.
The DSP56F801 includes many peripherals that are especially useful for applications such as motion
control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, and industrial control
for power, lighting, and automation.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The DSP56F801 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The DSP56F801 also provides one
external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F801 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Flash
(each programmable through the JTAG port) with 1K words of both program and data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main program and data flash memory areas. Both program and data flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the DSP56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
MOTOROLA
DSP56F801 Preliminary Technical Data
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