MC68020 Datasheet, PDF (247/306 Pages) Motorola, Inc – MICROPROCESSORS USERS MANUAL

8.2.11 Single-Operand Instructions
The single-operand instructions table indicates the number of clock periods needed for the
processor to perform the specified operation on the given addressing mode. Footnotes
indicate when it is necessary to add another table entry to calculate the total effective
execution time for the instruction. The total number of clock cycles is outside the
parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction
CLR
Dn
†
CLR
Mem
NEG
Dn
*
NEG
Mem
NEGX
Dn
*
NEGX
Mem
NOT
Dn
*
NOT
Mem
EXT
Dn
NBCD
Dn
Scc
Dn
†
Scc
Mem
TAS
Dn
†
TAS
Mem
*
TST
EA
*Add Fetch Effective Address Time
†Add Calculate Effective Address Time
Best Case
0(0/0/0)
3(0/0/1)
0(0/0/0)
3(0/0/1)
0(0/0/0)
3(0/0/1)
0(0/0/0)
3(0/0/1)
1(0/0/0)
6(0/0/0)
1(0/0/0)
6(0/0/1)
1(0/0/0)
12(1/0/1)
0(0/0/0)
Cache Case
2(0/0/0)
4(0/0/1)
2(0/0/0)
4(0/0/1)
2(0/0/0)
4(0/0/1)
2(0/0/0)
4(0/0/1)
4(0/0/0)
6(0/0/0)
4(0/0/0)
6(0/0/1)
4(0/0/0)
12(1/0/1)
2(0/0/0)
Worst Case
3(0/1/0)
6(0/1/1)
3(0/1/0)
6(0/1/1)
3(0/1/0)
6(0/1/1)
3(0/1/0)
6(0/1/1)
4(0/1/0)
6(0/1/0)
4(0/1/0)
6(0/1/1)
4(0/1/0)
13(1/1/1)
3(0/1/0)
MOTOROLA
M68020 USER’S MANUAL
8-33