MC74LVQ573 Datasheet, PDF (2/8 Pages) Motorola, Inc – LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MC74LVQ573
LOGIC DIAGRAM
1
OE
11
LE
2
D0
nLE
Q
D
3
D1
nLE
Q
D
4
D2
nLE
Q
D
5
D3
nLE
Q
D
6
D4
nLE
Q
D
7
D5
8
D6
nLE
Q
D
nLE
Q
D
9
D7
nLE
Q
D
19
O0
18
O1
17
O2
16
O3
15
O4
14
O5
13
O6
12
O7
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE
LE
Dn
Q
On
OPERATING MODE
L
H
H
H
L
H
L
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
h
H
H
L
L
l
L
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
NC
Hold; Read Latch
H
L
X
NC
Z
Hold; Disabled Outputs
H
H
H
H
H
H
L
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
L
h
H
H
L
l
L
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; L = Low Voltage Level; l = Low
Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; NC = No Change; X = High or Low Voltage Level and Transitions
are Acceptable; Z = High Impedance State; For ICC Reasons DO NOT FLOAT Inputs
MOTOROLA
2
ECLinPS and ECLinPS Lite
DL140 — Rev 3