MC74LVQ373 Datasheet, PDF (2/8 Pages) Motorola, Inc – LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MC74LVQ373
LOGIC DIAGRAM
1
OE
11
LE
3
D0
nLE
Q
D
4
D1
nLE
Q
D
7
D2
nLE
Q
D
8
D3
nLE
Q
D
13
D4
nLE
Q
D
14
D5
17
D6
nLE
Q
D
nLE
Q
D
18
D7
nLE
Q
D
2
O0
5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE
LE
Dn
Q
On
OPERATING MODE
L
H
H
H
L
H
L
L
H
L
Transparent (Latch Disabled); Read Latch
L
↓
h
H
H
L
↓
l
L
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
NC
Hold; Read Latch
H
L
X
NC
Z
Hold; Disabled Outputs
H
H
H
H
H
H
L
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
↓
h
H
H
↓
l
L
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; L = Low Voltage Level; l = Low
Voltage Level One Setup Time Prior to the Latch Enable High–to–Low Transition; NC = No Change; X = High or Low Voltage Level or Transitions
are Acceptable; Z = High Impedance State; ↓ = High–to–Low Transition; For ICC Reasons DO NOT FLOAT Inputs
MOTOROLA
2
LCX DATA
BR1339 — REV 2