MC74F299 Datasheet, PDF (2/5 Pages) Motorola, Inc – 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS

FUNCTION TABLE
MC74F299
Inputs
MR
S1
S0
L
X
X
H
H
H
H
L
H
H
H
L
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH clock transition.
CP
Response
X
Asynchronous Reset: Q0–Q7 = LOW
↑
Parallel Load: I/On Qn
↑
Shift Right: DS0 Q0, Q0 Q1, etc.
↑
Shift Left: DS7 Q7, Q7 Q6, etc.
X
Hold
FUNCTIONAL DESCRIPTION
The MC74F299 is an 8-bit universal shift/storage register
with 3-state outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel load
inputs and flip-flop outputs are multiplexed to reduce the total
number of package pins. Additional outputs are provided for
flip-flops Q0 and Q7 to allow easy serial cascading. A separate
active-LOW Master Reset is used to reset the register.
The MC74F299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S0 and S1,
as shown in the Function Table. All flip-flop outputs are
brought out through 3-state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
set-up and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE1 or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH
VIL
VIK
VOH
VOL
IIH
IIL
Input HIGH Voltage
2.0
V
Input LOW Voltage
0.8
V
Input Clamp Diode Voltage
–1.2
V
74
2.5
Q0/Q7
74
2.7
V
Output HIGH Voltage
74
2.7 3.4
I/O
V
74
2.4
Output LOW Voltage
Q0/Q7
I/O
0.5
V
0.5
Input HIGH Current
Q0/Q7
I/O
Q0/Q7
I/O
20
µA
70
0.1
mA
1.0
Input LOW Current
S0, S1
Other Inputs
–1.2
mA
– 0.6
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
VCC = MIN, IIN = –18 mA
IOH = –1.0 mA
VCC = 4.5 V
VCC = 4.75 V
IOH = – 3.0 mA
VCC = 4.75 V
VCC = 4.5 V
IOL = 20 mA
IOL = 24 mA
VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = MAX
VIN = 7.0 V
VIN = 5.5 V
VCC = MAX, VIN = 0.5 V
IOZH
IOZL
Off-State Output Current,
High-Level Voltage Applied
Off-State Output Current,
Low-Level Voltage Applied
70
µA
1.0 mA
– 0.6 mA
VCC = MAX
VOUT = 2.7 V
VOUT = 5.5 V
VCC = MAX, VOUT = 0.5 V
IOS
Output Short Circuit Current (Note 2)
ICC
Total Supply Current
– 60
–150 mA
95
mA
VCC = MAX
VOUT = 0 V
OE = HIGH, CP = HIGH
NOTES:
1. For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at one time, nor for more than 1 second.
FAST AND LS TTL DATA
4-243