MC74AC161 Datasheet, PDF (2/12 Pages) ON Semiconductor – Synchronous Presettable Binary Counter

MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
FUNCTIONAL DESCRIPTION
The MC74AC161/74ACT161 and MC74AC163/74ACT163
count modulo-16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip-flops are driven in parallel through a clock buffer. Thus all
changes of the Q outputs (except due to Master Reset of the
′161) occur as a result of, and synchronous with, the
LOW-to-HIGH transition of the CP input signal. The circuits
have four fundamental modes of operation, in order of
precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count-up and hold. Five control inputs —
Master Reset (MR, ′161), Synchronous Reset (SR, ′163),
Parallel Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET)  determine the mode of operation, as
shown in the Mode Select Table. A LOW signal on MR
overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the next
rising edge of CP. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be loaded
into the flip-flops on the next rising edge of CP. With PE and MR
(′161) or SR (′163) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The MC74AC161/74ACT161 and MC74AC163/74ACT163
use D-type edge-triggered flip-flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways. Please refer to the
MC74AC568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers.
Logic Equations: Count Enable = CEP•CET•PE
TC = Q0•Q1•Q2•Q3•CET
MODE SELECT TABLE
*SR PE CET
L
X
X
H
L
X
H
H
H
H
H
L
H
H
X
*For ′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
CEP
X
X
H
X
L
Action on the Rising
Clock Edge ( )
Reset (Clear)
Load (Pn → Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
LOGIC DIAGRAM
P0
P1
PE
′161 ′163
CEP
CET
′163
ONLY
STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12 11 10 9
8
P2
P3
TC
CP
MR ′161
SR ′163
CP ′161
ONLY
Q0
CP
D CP D
CD _{Q Q}
Q0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
Q0
Q1
Q2
Q3
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
FACT DATA
5-2