MC5474F164 Datasheet, PDF (2/3 Pages) Motorola, Inc – 8-BIT SERIAL-IN, PARALLEL-OUT SHIFT REGISTER

MC54/74F164
LOGIC DIAGRAM
A
B
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CD
CD
CD
CD
CD
CD
CD
CD
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FUNCTIONAL DESCRIPTION
The F164 is an edge-triggered 8-bit shift register with se-
rial data entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A or B); ei-
ther of these inputs can be used as an active HIGH Enable
for data entry through the other input. An unused input must
be tied HIGH.
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
TA
Supply Voltage
Operating Ambient Temperature Range
IOH
Output Current  High
IOL
Output Current  Low
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the logical
AND of the two data inputs (A • B) that existed before the rising
clock edge. A LOW level on the Master Reset (MR) input over-
rides all other inputs and clears the register asynchronously,
forcing all Q outputs LOW.
Min
Typ
Max
Unit
54, 74
4.5
5.0
5.5
V
54
–55
25
125
°C
74
0
25
70
54, 74
–1.0
mA
54, 74
20
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
VIL
VIK
VOH
VOL
IIH
IIL
IOS
ICC
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
2.0
54, 74 2.5
74
2.7
Input LOW Current
Output Short Circuit Current (Note 2)
–60
Power Supply Current
V
Guaranteed Input HIGH Voltage
0.8
V
Guaranteed Input LOW Voltage
–1.2
V
VCC = MIN, IIN = –18 mA
V
IOH = –1.0 mA
VCC = MIN
V
IOH = –1.0 mA
VCC = 4.75 V
0.5
V
IOL = 20 mA
VCC = MIN
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA VCC = MAX, VIN = 7.0 V
–0.6
mA VCC = MAX, VIN = 0.5 V
–150
mA VCC = MAX, VOUT = 0 V
35
55
mA A, B = GND, VCC = MAX
CP = HIGH, MR = GND
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-80