MC145200 Datasheet, PDF (18/23 Pages) Motorola, Inc – 2.0 GHz PLL Frequency Synthesizers

PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
(A)
PDout
VCO
R
C
ω_n =
K_φ KVCO
NC
R
ζ= ₂
K_φ KVCOC
N
=
ω_nRC
2
1 + sRC
Z(s) = _sC
NOTE:
For (A), using K_φ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/
filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ω_c = 1/RC′ should be
chosen such that ω_n is not significantly affected.
(B)
φ_R
φ_V
R2
R1
C
–
A
VCO
+
R1
R2
C
ω_n =
K_φ KVCO
NCR1
ω_nR2C
ζ=
2
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) = ^{R2sC + 1}
R1sC
NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the
midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not
significantly affect ω_n.
* The φ_R and φ_V outputs are fed to an external combiner/loop filter. The φ_R and φ_V outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K_φ (Phase Detector Gain) = IPDout / 2π amps per radian for PDout
K_φ (Phase Detector Gain) = VPD / 2π volts per radian for φ_V and φ_R
KVCO
(VCO
Transfer
Function)
=
2π∆fVCO
∆VVCO
radians per volt
For a nominal design starting point, the user might consider a damping factor ζ≈0.7 and a natural loop frequency ω_n ≈ (2πfR/50) where
fR is the frequency at the phase detector input. Larger ω_n values result in faster loop lock times and, for similar sideband filtering, higher
fR–related VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This addi-
tional filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253/D, An Improved PLL Design Method Without ω_n and ζ, Motorola Semiconductor Products, Inc., 1995.
MC145200•MC145201
18
MOTOROLA