M68HC05 Datasheet, PDF (170/222 Pages) Motorola, Inc – M68HC05 MICROCONTROLLERS

Table 12-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
MSB
0
1
2
3
4
5
6
7
LSB
5
5
3
5
3
3
6
5
0
BRSET0 BSET0
BRA
NEG
NEGA NEGX
NEG
NEG
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
1
BRCLR0 BCLR0
BRN
3
DIR 2
DIR 2 REL
1
5
5
3
2
BRSET1 BSET1
BHI
3
DIR 2
DIR 2 REL
11
MUL
1
INH
5
5
3
5
3
3
6
5
3
BRCLR1 BCLR1
BLS
COM
COMA COMX
COM
COM
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
4
BRSET2 BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
BRCLR2 BCLR2 BCS/BLO
3
DIR 2
DIR 2 REL
5
5
3
5
3
3
6
5
6
BRSET3 BSET3
BNE
ROR
RORA RORX
ROR
ROR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
7
BRCLR3 BCLR3
BEQ
ASR
ASRA ASRX
ASR
ASR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
8
BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
9
BRCLR4 BCLR4 BHCS
ROL
ROLA ROLX
ROL
ROL
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
8
9
RTI
INH
6
RTS
INH
10
SWI
INH
1
1
1
9
2
2
2
2
2
2
2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
A
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
B
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
C
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
D
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
E
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
F
MSB
LSB
3
SUB
0
IX
3
CMP
1
IX
3
SBC
2
IX
3
CPX
3
IX
3
AND
4
IX
3
BIT
5
IX
3
LDA
6
IX
4
STA
7
IX
3
EOR
8
IX
3
ADC
9
IX
5
5
3
5
3
3
6
5
A
BRSET5 BSET5
BPL
DEC
DECA DECX
DEC
DEC
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
2
3
4
5
4
3
CLI
ORA
ORA
ORA
ORA
ORA
ORA
A
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
B BRCLR5 BCLR5
BMI
3
DIR 2
DIR 2 REL
2
2
3
4
5
4
3
SEI
ADD
ADD
ADD
ADD
ADD
ADD
B
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
C
BRSET6 BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
RSP
1
INH
2
3
4
3
2
JMP
JMP
JMP
JMP
JMP
C
2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
4
3
3
5
4
D BRCLR6 BCLR6 BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
6
5
6
7
6
5
NOP
BSR
JSR
JSR
JSR
JSR
JSR
D
1
INH 2 REL 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
E
BRSET7 BSET7
BIL
3
DIR 2
DIR 2 REL
2
STOP
1
INH
2
3
4
5
4
3
LDX
LDX
LDX
LDX
LDX
LDX
E
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
2
2
F BRCLR7 BCLR7
BIH
CLR
CLRA CLRX
CLR
CLR
WAIT
TXA
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH 1
INH
4
5
6
5
4
STX
STX
STX
STX
STX
F
2
DIR 3 EXT 3
IX2 2
IX1 1
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB
0
LSB
MSB of Opcode in Hexadecimal
5 Number of Cycles
LSB of Opcode in Hexadecimal 0
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode