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MCM69L738A Datasheet, PDF (17/20 Pages) Motorola, Inc – 4M Late Write 2.5 V I/O | |||
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STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM outputs to HighâZ state. NOT IEEE 1149.1 COMPLIANT.
IDCODE
001** Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE / PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
Places bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLEâZ
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM output drivers to HighâZ state.
* Instruction codes expressed in binary, MSB on left, LSB on right.
** Default instruction automatically loaded at powerâup and in testâlogicâreset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
TESTâLOGIC
1
RESET
0
RUNâTEST/
1
0
IDLE
SELECT
DRâSCAN
1
0
1
CAPTUREâDR
0
SHIFTâDR
0
1
1
EXIT1âDR
0
PAUSEâDR
0
1
0
EXIT2âDR
1
UPDATEâDR
1
0
SELECT
IRâSCAN
1
0
1
CAPTUREâIR
0
SHIFTâIR
0
1
1
EXIT1âIR
0
PAUSEâIR
0
1
0
EXIT2âIR
1
UPDATEâIR
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MOTOROLA FAST SRAM
MCM69L738Aâ¢MCM69L820A
17
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