MC44603 Datasheet, PDF (17/24 Pages) ON Semiconductor – MIXED FREQUENCY MODE GREENLINE PWM CONTROLLER

MC44603
Maximum Duty Cycle and Soft–Start Control
Maximum duty cycle can be limited to values less than
80% by utilizing the Dmax and soft–start control. As depicted
in Figure 42, the Pin 11 voltage is compared to the oscillator
sawtooth.
Figure 42. Dmax and Soft–Start
Figure 45. Foldback Characteristic
Vout
Ipk _max
VO
Nominal
Vref
0.4 Iref
11
DZ 2.4 V ^CDmax
Output
Control
Output
Dmax ^Drive
VCC
Vdisable2
New Startup
Sequence Initiated
Iout
Overload
Soft–Start
Capacitor
VOSC
Oscillator
Figure 43. Maximum Duty Cycle Control
Voltage
Dmax
Pin 11
VCT
(Pin 10)
Using the internal current source (0.4 Iref), the Pin 11
voltage can easily be set by connecting a resistor to this pin.
If a capacitor is connected to Pin 11, the voltage increases
from 0 to its maximum value progressively (refer to Figure
44), thereby, implementing a soft–start. The soft–start
capacitor is discharged internally when the VCC (Pin 1)
voltage drops below 9.0 V.
Figure 44. Different Possible Uses of Pin 11
Pin 11 _{R Connected to Pin 11}
C
C // R
I = 0.4 Iref
RI
VZ
VZ
RI
τ = RC
If no external component is connected to Pin 11, an
internal zener diode clamps the Pin 11 voltage to a value VZ
that is higher than the oscillator peak value, disabling
soft–start and maximum duty cycle limitation.
Foldback
As depicted in Fgure 32, the foldback input (Pin 5) can be
used to reduce the maximum VCS value, providing foldback
protection. The foldback arrangement is a programmable
peak current limitation.
If the output load is increased, the required converter peak
current becomes higher and VCS increases until it reaches its
maximum value (normally, VCS _max = 1.0 V).
Then, if the output load keeps on increasing, the system is
unable to supply enough energy to maintain the output
voltages in regulation. Consequently, the decreasing output
can be applied to Pin 5, in order to limit the maximum peak
current. In this way, the well known foldback characteristic
can be obtained (refer to Figure 45).
NOTE: Foldback is disabled by connecting Pin 5 to VCC.
Overvoltage Protection
The overvoltage arrangement consists of a comparator
that compares the Pin 6 voltage to Vref (2.5 V) (refer to
Figure 46).
If no external component is connected to Pin 6, the
ǒ ₎ Ǔ ^{comparator noninverting input voltage is nearly equal to:}
11.6
k2W^.0
kW
2.0
kW
x VCC
ǒ ₎ Ǔ w ^{The comparator output is high when:}
11.6
k2W^.0
kW
2.0
kW
x VCC
2.5 V
à w VCC 17 V
A delay latch (2.0 µs) is incorporated in order to sense
overvoltages that last at least 2.0 µs.
If this condition is achieved, VOVP _out, the delay latch
output, becomes high. As this level is brought back to the
input through an OR gate, VOVP _out remains high (disabling
the IC output) until Vref is disabled.
Consequently, when an overvoltage longer than 2.0 µs is
detected, the output is disabled until VCC is removed and
then re–applied.
The VCC is connected after Vref has reached steady state
in order to limit the circuit startup consumption.
The overvoltage section is enabled 5.0 µs after the
regulator has started to allow the reference Vref to stabilize.
By connecting an external resistor to Pin 6, the threshold
VCC level can be changed.
Figure 46. Overvoltage Protection
Vref
VCC
Out
T
Delay τ 5.0 µs
0 ^{2.5 V}
In
VOVP
External ⁶
Resistor
11.6 k ^Enable
2.0 k ^COVLO
2.5 V
(Vref)
In τ Out
Delay
VOVP _out
2.0 µs
(If VOVP _out = 1.0,
the Output is Disabled)
MOTOROLA ANALOG IC DEVICE DATA
17