MC33689 Datasheet, PDF (16/18 Pages) Motorola, Inc – System Basis Chip with LIN transceiver

Freescale SMeC3m36i8c9onductor, Inc.
6 SPI INTERFACE AND REGISTER DESCRIPTION
6.1
Data format description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO _{D7 D6 D5 D4 D3 D2 D1 D0}
MOSI
The SPI is an 8 bits SPI. All bits are data bytes. The MSB is send first. The minimum time between two rising edges on the
CSB pin is 15us.
During an SPI communication the state of MISO reports the state of the SBC, at time of CSB high to low transitions. The status
flag are latched at CSB high to low transitions.
Following tables describe the SPI register bit meaning, “reset value” and “bit reset condition”.
Write Reset
value
Write Reset
condition
D7
W LINSL2
R
INT
source
D6
LINSL1
LINWU
or
LINFAIL
0
0
POR,
POR,
RESET RESET
D5
LIN-PU
VSOV
0
POR
D4
HS3
VSUV
BATFAIL
(note1)
D3
HS2
VddT
D2
D1
D0
HS1 Mode2 Mode1
HSst
L2
L1
0
0
0
-
-
POR,
RESET
POR, POR,
RESET RESET
Note 1: The first SPI read, after reset, returns the BATFAIL flag state on bit D4.
D7 signals INT source. After INT occur, D7 read as a “1” means other bits report the INT source. D7 read as a “0” mean no INT
occurred and other bit report real time status.
6.2
6.2.1
Write control bits:
Mode control bits:
Mode 2
0
0
1
1
Mode 1
0
1
0
1
6.2.2 High side switches control bits:
Description
Sleep mode
Stop mode
Normal mode + W/D clear
Normal mode
HS1
Description
HS2
Description
HS3
0
HS1 off
0
HS2 off
0
1
HS1 on (if IN = 1)
1
HS2 on (if IN = 1)
1
6.2.3 LIN pull up termination control bits:
Description
HS3 off
HS3 on
LIN-PU
0
1
Description
30k pull up connected in sleep and stop mode
30k pull up disconnected in sleep and stop mode
MC33689
16
For More Information On This Product,
Go to: www.freescale.com