MC13109A Datasheet, PDF (16/28 Pages) Motorola, Inc – UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC

Figure 7. Enable Timing Requirement
50%
Clk
tsuEC
Last
Clock
50%
First
Clock
trec
MC13109A
modes; Inactive, Standby, Rx, and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Figure 9. Microprocessor Serial Interface
Power–Up Delay
50%
50%
2.0 V
EN
Previous Data Latch
VCC
tpuMPU
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 8 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
Data,
Clk, EN
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Status Out
This is a digital output which indicates whether the latch
registers have been reset to their power–up default values.
Latch power–up default values are given in Figure 28. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the “Status Out”
Figure 8. Microprocessor Interface Programming
pin will indicate this to the MPU so it can reload the correct
Data
EN
Data
Mode Diagrams
MSB
8–Bit Address
LSB
Address Register Programming Mode
MSB
16–Bit Data
LSB
information into the latch registers.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Figure 10. Status Out Operation}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Latch
Status Out
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Status Latch Register Bits}
Logic Level
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Latch bits not at power–up default value
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Latch bits at power–up default value
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^Latch
EN
Data Register Programming Mode
The MPU serial interface is fully operational within 100 µs
after the power supply has reached its minimum level during
power–up (See Figure 9). The MPU Interface shift registers
and data latches are operational in all four power saving
Data Registers
Figure 11 shows the data latch registers and addresses
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
“Don’t Care” bits can be loaded into the shift register first if
8–Bit bytes of data are loaded.
16
MOTOROLA RF/IF DEVICE DATA