68HC908RF Datasheet, PDF (159/188 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
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Break Module (BRK)
13.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status bits can be
cleared during the break state. The BCFE bit in the SIM break flag control register
(BFCR) enables software to clear status bits during the break state. (See 10.7.3
SIM Break Flag Control Register and the Break Interrupts subsection for each
module.)
13.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If
the break address register match occurs on the last cycle of a CPU instruction, the
break interrupt begins immediately.
13.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
13.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_HI is present on the RST pin.
13.2.2 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
13.2.2.1 Wait Mode
If enabled, the break module is active in wait mode.
13.2.2.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect
break module register states.
MC68HC908RF2 — Rev. 4.0
MOTOROLA
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Data Sheet
159