M68HC11ERG Datasheet, PDF (15/60 Pages) Motorola, Inc – M68HC11E Series Programming Reference Guide

M68HC11ERG/AD
Instruction Set
Table 1. Instruction Set (Sheet 3 of 8)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Condition Codes
Opcode Operand Cycles S X H I N Z V C
BVS (rel)
Branch if
Overflow Set
?V=1
REL
29 rr
3
————————
CBA
Compare A to B
A–B
INH
11
—
2
———— ∆ ∆ ∆ ∆
CLC
Clear Carry Bit
0⇒C
INH
0C
—
2
——————— 0
CLI
Clear Interrupt
Mask
0⇒I
INH
0E
—
2
——— 0 ————
CLR (opr)
Clear Memory
Byte
0⇒M
EXT
IND,X
IND,Y 18
7F hh ll
6F ff
6F ff
6
———— 0 1 0 0
6
7
CLRA
Clear
Accumulator A
0⇒A
A
INH
4F
—
2
———— 0 1 0 0
CLRB
Clear
Accumulator B
0⇒B
B
INH
5F
—
2
———— 0 1 0 0
CLV
Clear Overflow
Flag
0⇒V
INH
0A
—
2
—————— 0 —
CMPA (opr) Compare A to
Memory
A–M
A
IMM
81 ii
A
DIR
91 dd
A
EXT
B1 hh ll
A
IND,X
A1 ff
A
IND,Y 18
A1 ff
2
———— ∆ ∆ ∆ ∆
3
4
4
5
CMPB (opr) Compare B to
Memory
B–M
B
IMM
C1 ii
B
DIR
D1 dd
B
EXT
F1 hh ll
B
IND,X
E1 ff
B
IND,Y 18
E1 ff
2
———— ∆ ∆ ∆ ∆
3
4
4
5
COM (opr)
Ones
Complement
Memory Byte
$FF – M ⇒ M
EXT
IND,X
IND,Y 18
73 hh ll
63 ff
63 ff
6
———— ∆ ∆ 0 1
6
7
COMA
Ones
Complement
A
$FF – A ⇒ A
A
INH
43
—
2
———— ∆ ∆ 0 1
COMB
Ones
Complement
B
$FF – B ⇒ B
B
INH
53
—
2
———— ∆ ∆ 0 1
CPD (opr)
Compare D to
Memory 16-Bit
D–M:M +1
IMM
1A 83 jj kk
DIR
1A 93 dd
EXT
1A B3 hh ll
IND,X 1A A3 ff
IND,Y CD A3 ff
5
———— ∆ ∆ ∆ ∆
6
7
7
7
CPX (opr)
Compare X to
Memory 16-Bit
IX – M : M + 1
IMM
8C jj kk
DIR
9C dd
EXT
BC hh ll
IND,X
AC ff
IND,Y CD AC ff
4
———— ∆ ∆ ∆ ∆
5
6
6
7
CPY (opr)
Compare Y to
Memory 16-Bit
IY – M : M + 1
IMM
18
DIR
18
EXT
18
IND,X 1A
IND,Y 18
8C jj kk
9C dd
BC hh ll
AC ff
AC ff
5
———— ∆ ∆ ∆ ∆
6
7
7
7
DAA
Decimal Adjust Adjust Sum to BCD
INH
A
19
—
2
———— ∆ ∆ ∆ ∆
DEC (opr)
Decrement
Memory Byte
M–1⇒M
EXT
IND,X
IND,Y 18
7A hh ll
6A ff
6A ff
6
———— ∆ ∆ ∆ —
6
7
DECA
Decrement
Accumulator
A
A–1⇒A
A
INH
4A
—
2
———— ∆ ∆ ∆ —
DECB
Decrement
Accumulator
B
B–1⇒B
B
INH
5A
—
2
———— ∆ ∆ ∆ —
MOTOROLA
M68HC11E Series Programming Reference Guide
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