MCM64Z834 Datasheet, PDF (14/34 Pages) Motorola, Inc – 256K x 36 and 512K x 18 Bit ZBT Fast Static RAM

Freescale Semiconductor, Inc.
INTERMEDIATE
INTERMEDIATE
D
B
HIGH–Z
R
W
INTERMEDIATE
INTERMEDIATE
R
B
D
W
DATA OUT
(Q VALID)
INTERMEDIATE
DW
B
HIGH–Z
(DATA IN)
R
INTERMEDIATE
KEY:
CURRENT
STATE (n)
INTERMEDIATE
STATE (n + 1)
NEXT STATE
TRANSITION
TRANSITION ^{(n + 2)}
ƒ
INPUT
COMMAND
CODE
NOTES:
1. Input command codes (D, W, R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
Figure 6. Data I/O State Diagram (Pipelined)
STATE
CK
COMMAND
CODE
n
n+1
n+2
n+3
ƒ
DQ
STATE NAME
CURRENT INTERMEDIATE
STATE
STATE
NEXT
STATE
Figure 7. State Definitions for I/O State Diagram (Pipelined)
MCM64Z834•MCM64Z916
14
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MOTOROLA FAST SRAM