MC44251 Datasheet, PDF (12/18 Pages) Motorola, Inc – Triple 8-Bit Video ADC Three-State Outputs

APPLICATION INFORMATION
PCB DESIGN
To maximize the performance of the MC44251, noise
should be kept to a minimum. Good printed circuit board de-
sign will enhance the operation of the MC44251. Separate
analog and digital grounds will reduce noise and conversion
errors. In addition, separate filters on analog VCC and digital
VDD will also help to minimize noise and conversion errors.
Sufficient decoupling and short leads will also improve per-
formance.
When designing mixed analog/digital printed circuit
boards, separate ground planes for digital ground and analog
ground should be employed. Large switching currents gener-
ated by digital circuits will be amplified by analog circuitry
and can quickly make a circuit unusable. Care should be tak-
en to ensure analog ground does not inadvertently become
part of the digital ground. The analog and digital grounds
should be connected together at only one point. This is usu-
ally at or near where power enters the printed circuit board.
Additionally, when interconnecting several printed circuit
boards together, care must be taken to ensure that cabling
does not interconnect digital and analog grounds together to
produce a path for digital switching currents through analog
ground.
When using any device with the performance and speed of
the MC44251, ground planes are essential. Loosely inter-
connected traces and/or random areas of ground strewn
around the printed circuit board are inadequate for high per-
formance circuitry. While distribution of VDD and VCC can be
done by bussing, to do so with the ground system is disas-
trous.
An inch long conductor is an 18 nH inductor. The cross
sectional area of the conductor affects the exact value of the
inductance, but for most PCB traces this is approximately
correct. If the ground system is composed of traces or
clumps of ground loosely interconnected, it will be inductive.
The amount of inductance will be proportional to the length of
the conductors making up the ground. This inductance can-
not be decoupled away. It must be designed out.
A CMOS device exhibits a characteristic input capacitance
of about 10 pF. If this gate is driven by a digital signal that
switches 2.5 V in a period of 5 ns, the equation for the aver-
age current flowing during the switching time will be:
IAV = Cdv/dt.
A voltage change of 2.5 V in 5 ns requires an average cur-
rent of 5 mA. If we assume a linear ramp starting from zero,
the total change in current will be 10 mA. The change in cur-
rent per nanosecond per gate can be found by dividing the
change in current by the time
10 mA/5 ns = 2 mA/ns.
For a device with 16 outputs driving one gate for each out-
put,
di/dt = 16 × 2 mA/ns = 32 mA/ns.
If the above 1–inch wire is in this current path, then the
voltage dropped across it can be found from the formula
V = Ldi/dt = 18 nH × 32 mA/ns = 0.576 V.
If the inductor is in the ground system, it is in the signal
path. The voltage generated by the switching currents
through this inductor will be added to the signal. At best it will
be superimposed on the analog signal as unwanted noise. At
worst, it can render the entire circuit unusable. Even the digi-
tal signal path is not immune to this type of signal. It can false
trigger clock circuits causing timing errors, confuse compara-
tor type circuits, and cause digital signals to be misinter-
preted as wrong values.
When laying out the PCB, use electrolytic capacitors of
sufficient size at the power input to the printed circuit board.
Adding low ESR decoupling capacitors of about 0.1 µF
capacitance across VCC and/or VDD at each device will help
reduce noise in general and ESD susceptibility. Implementa-
tion of a good ground plane ground system can all but elimi-
nate the type of noise described above.
To summarize, use sufficient electrolytic capacitor filtering,
make separate ground planes for analog ground and digital
ground, tie these grounds together at one and only one point,
keep the ground planes as continuous and unbroken as pos-
sible, use low ESR capacitors of about 0.1 µF capacitance
on VCC and VDD at each device, and keep all leads as short
as possible.
EMI SUPPRESSION
When using ICs in or near television receiver circuits, EMI
(electromagnetic interference) and subsequent unwanted
display artifacts and distortion are probable unless adequate
EMI suppression is implemented. A common misconception
is that some offending digital device is the culprit. This is er-
roneous in that an IC itself has insufficient surface area to
produce sufficient radiation. The device, while it is the gener-
ator of interfering signals, must be coupled to an antenna be-
fore EMI is radiated. The source for the EMI is not the IC
which generates the offending signals but rather the circuitry
which is attached to the IC.
Potential EMI signals are generated by all digital devices.
Whether they become a nuisance is dependent upon their
frequency and whether they have a sufficient antenna. The
frequency and number of these signals is affected by both
circuit design within the IC and the manufacturing process.
Device speed is also a major contributor of potential EMI. Be-
cause the design is determined by the anticipated applica-
tion, the manufacturing process is fixed and the drive for
speed ever increasing, the only effective point to implement
EMI suppression is in the PC board design. The PC board
usually is the antenna which radiates the EMI. The most effi-
cient method of minimizing EMI radiation is to minimize the
efficiency of this antenna.
The most common cause of inadequate EMI suppression
lies with the ground system of the suspected digital devices.
As pointed out previously, di/dt transitions can be significant
in digital circuits. If the di/dt transitions appear in the ground
system and the ground system is inductive, the harmonics
present in these transitions are a source of potential EMI sig-
nals. The unfortunate result of putting digital devices on a
reactive ground system is guaranteed EMI problems.
The area which should be addressed first as a potential
EMI source is the ground. Without an adequate ground sys-
tem, EMI cannot be effectively reduced by decoupling. If at
all possible, the ground should be a complete unbroken
plane. Figure 12 shows two examples of relieving ground
around device pins. When relieving vias and plated through
holes, large areas of ground loss should be avoided. When
MC44251
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MOTOROLA