M68HC11E Datasheet, PDF (118/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
serial shift register. The output of the serial shift register is applied to TxD as long
as transmission is in progress or the transmit enable (TE) bit of serial
communication control register 2 (SCCR2) is set. The block diagram, Figure 7-1,
shows the transmit serial shift register and the buffer logic at the top of the figure.
TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
WRITE ONLY
10 (11) - BIT Tx SHIFT REGISTER
H (8) 7 6 5 4 3 2 1 0 L
DDD1
PIN BUFFER
AND CONTROL
SEE NOTE
PD1
TxD
8
SCCR1 SCI CONTROL 1
TRANSMITTER
CONTROL LOGIC
FORCE PIN
DIRECTION (OUT)
SCSR INTERRUPT STATUS
TDRE
TIE
TC
TCIE
8
8
SCCR2 SCI CONTROL 2
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting TxD to a PC.
Figure 7-1. SCI Transmitter Block Diagram
Data Sheet
118
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
M68HC11E Family — Rev. 5
MOTOROLA