MC146805E2_1 Datasheet, PDF (11/36 Pages) Motorola, Inc – 8-BIT MICROPROCESSOR UNIT

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Freescale Semiconductor, Inc.
FUNCTIONAL PIN DESCRIPTION
BO-B7 (ADDRESS/DATA BUS)
VDD AND Vss
The BO-B7 bidirectional lines constitute the lower order
addresses and data. These lines are multiplexed, with ad-
VDD and VSS provide power to the chip. VDD provides
dress present at address strobe time and data present at data
power and VSS is ground.
strobe time, When in the data mode, these lines are bidirec-
tional, transferring data to and from memory and peripheral
~Q (MASKABLE INTERRUPT REQUEST)
devices as indicated by the R/~pin. As outputs in either the
IRQ is both a level-sensitive and edge-sensitive input
which can be used to request an interrupt sequence. The
data or address modes, these lines are capable of driving one
standard TTL load and 130 pF,
M PU completes the current instruction before it responds to
the request, If IRQ is low and the interrupt mask bit (1bit) in
the condition code register is clear, the MPU begins an inter-
Oscl, 0SC2
.!_A,. _),,),,
..:$,,Yi,~.:.,..’>,:..kt...:,.,)i,’
The MC146805E2 provides for two types o~~$~!~qtor in-
rupt sequence at the end of the current instruction, The in-
puts – crystal circuit or external clock. T~$~$$bscillator
terrupt circuit recognizes both a “wire ORed” level as well as
pulses on the IRQ line (see Interrupt section for more
pins are used to interface to a crystal C$Lt~,F.,m,,!I*N~\.s\+paSshown in
Figure 5. If an external clock is used, it~B%t@ connected to
details). IRQ requires an external resistor to VDD for “wire
OSCI. The input at these pins is div~@{~five to form the
OR” operation.
cycle rate seen on the AS and D~:~f~.me frequency range
is specified by fosc. The OS~l ‘?~,,,@~stransitions relation-
RESET
The RESET input is not required for start-up but can be
used to reset the MPU internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
ships are provided in FigU{~~~ fot system designs using
oscillators slower than 5 ~~~!?$$
,<,p.~,,,0~,-.1~‘,,..,:..*::
CRYSTAL – Theq[@~~@Shown in Figure 5 is recommend-
ed when using a wta.~he internal oscillator is designed to
interface wit~.s~,,n AT-cut parallel resonant quartz crystal
TIMER
The TIMER input is used for clocking the on-chip timer,
Refer to Timer section for a detailed description.
resonator in-ttigtif$equency range specified for fosc in the
electrical~$ti~~~~~eristics table. An external CMOS oscillator
is recw,%:~#ed when crystals outside the specified ranges
are $~i:~e used, The crystal and components should be
AS (ADDRESS STROBE)
Address strobe (AS) is an output strobe used to indicate
M$unte&as close as possible to the input pins to minimize
:@.,~\..dT~<~:iut ^{distortion and start-up stabilization time,}
the presence of an address on the 8-bit multiplexed bus. The ::!*“!+w$$~EXTERNAL _{CLOCK – An external clock should be ap-}
AS line is used to demultiplex the eight least significant ad- ‘t$,.~.~~$: _{~lied to the OSCI input with the 0SC2 input not connected,}
dress bits from the data bus, A latch controlled by address “~~ _{as shown in Figure 10.}
strobe should capture addresses on the negative edge,.+Thi@$’
output is capable of driving one standard TTL load 4’&I130
LI (LOAD INSTRUCTION)
DS (DATA STROBE)
,$t^~,^Li,^,%^,;^,:,^@,^$.$K^~,\i?: :’~
$V1..t,1,,.,*!3},,,.,,,..
This output is used to transfer data t@:~#$&& a peripheral
or memory. DS occurs anytime the M~$U’@8s a data read or
write. DS also occurs when the ~~~ ,{b’~k a data transfer to
or from the MPU internal mw@.W,t%efer to Table 2 and
Figure 4 for timing charact6ri$J::$This output is capablebf
driving one standard T~&k~&and 130 pF. DS is a con-
tinuous signal at fosc,k+ 5~,#n the MPU is not in the WAIT
oopr cSodTeOPbystetast,e,..,.\~t-+S.\.~w<\@‘.:,.,,,‘.~$,:&,.>:.,’iy@l~<b?u$s$~cycles ^{are redundant reads of}
Rl~ (READ~t&~Tt)
The ~~~~u~ut is used to indicate the direction of data
trao:,f~~fo~@6th internal memory and 1/O registers, and ex-
ter..:n,Jg~($’{~p,.~...t~heral devices and memories. This output is used
,<to@&ate to a selected peripheral whether the M PU is going
‘~~k~~~d or write data on the next data strobe (R/~
I&_= processor write; R/~ high = processor read). The
R/W output is capable of driving one standard TTL load and
130 pF. The normal standby state is read (high).
A8-A12 (HIGH ORDER ADDRESS LINES)
The A8-A12 output lines constitute the higher order non-
multiplexed addresses. Each output line is capable of driving
one standard TTL load and 130 pF.
This output is used to indicate tha~ a fetch of the next op-
code is in progress. LI remains low during an external or
timer interrupt. The LI output is used only for certain debug-
ging and test systems. For normal operations this pin is not
connected. The LI output is capable of driving two standard
LSTTL loads and 50 pF. This signal overlaps data strobe,
PAO-PA7
These eight pins constitute input/output port A. Each line
is individually programmed to be either an input or output
under software control via its data direction register as
shown in Figure Ii(b). An 1/0 pin is programmed as an out-
put when the corresponding DDR bit is set to a “l”, and as
an input when it is set to a “O’. In the output mode the bits
are latched and appear on the corresponding output pins. An
M PU read of the port bits programmed as outputs reflects
the last value written to that location, When programmed as
an input, the input data Mt(s) are not latched. An MPU read
of the port bits programmed as inputs reflects the current
status of the corresponding input pins. The 1/0 port timing is
shown in Figure 3, See typical 1/0 port circuitry in Figure 11.
During a power-on reset or external reset, all lines are con-
figured as inputs (zero in data direction register). The output
port register is not initialized by reset. The TTL compatible
three-state output buffers are capable of driving one stan-
dard TTL load and 50 pF. The DDR is a re~d/write register.
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