68HC908GR Datasheet, PDF (109/408 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
Functional Description
c. In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
d. In the PLL VCO range select register (PMRS), program the
binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program
the binary coded equivalent of R.
Table 7-1 provides numeric examples (numbers are in hexadecimal
notation):
f_BUS
2.0 MHz
2.4576 MHz
2.5 MHz
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
Table 7-1. Numeric Example
f_RCLK
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
R
N
PE
L
1
F5
0 0 D1
1
12C
01
80
1
132
01
83
1
1E9
0 1 D1
1
258
02
80
1
263
02
82
1
384
0 2 C0
1
3D1
0 2 D0
7.4.7 Special Programming Exceptions
The programming method described in Programming the PLL does not
account for three possible exceptions. A value of 0 for R, N, or L is
meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See Base Clock Selector Circuit.)
MC68HC908GR8 — Rev 4.0
MOTOROLA
Clock Generator Module (CGMC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
109