SN54LS73A Datasheet, PDF (1/3 Pages) Motorola, Inc – DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will per-
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
Q
13 (8)
K
3 (10)
LOGIC DIAGRAM (Each Flip-Flop)
1 (15)
CLOCK (CP)
Q
12 (9)
CLEAR
2 (6)
J
14 (7)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
CD
J
K
OUTPUTS
Q
Q
Reset (Clear)
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
X
X
L
H
H
h
h
q
q
H
l
h
L
H
H
h
l
H
L
H
l
l
q
q
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition.
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
14 J
Q 12 7 J
Q9
1 CP
5 CP
3 K _CD Q 13 10 K _CD Q 8
2
6
VCC = PIN 4
GND = PIN 11
FAST AND LS TTL DATA
5-68