SN54LS375 Datasheet, PDF (1/5 Pages) Motorola, Inc – 4-BIT D LATCH

4-BIT D LATCH
The SN54/ 74LS375 is a 4-Bit D-Type Latch for use as temporary storage
for binary information between processing limits and input /output or indicator
units. When the Enable (E) is HIGH, information present at the D input will be
transferred to the Q output and, if E is HIGH, the Q output will follow the input.
When E goes LOW, the information present at the D input prior to its setup time
will be retained at the Q outputs.
VCC
16
CONNECTION DIAGRAM DIP (TOP VIEW)
D3
Q3
Q3
E2,3
Q2
Q2
D2
15
14
13
12
11
10
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
D0
2
Q0
3
Q0
4
E0,1
5
Q1
6
Q1
7
D1
8
GND
TRUTH TABLE
(Each latch)
tn tn+1
D
Q
H
H
L
L
NOTES:
tn = bit time before enable
negative-going transition.
tn+1 = bit time after enable
negative-going transition.
PIN NAMES
LOADING (Note a)
HIGH
LOW
D1 – D4
Data Inputs
0.5 U.L.
0.25 U.L.
E0 _{– 1}
E2 _{– 3}
Q1 – Q4
Q1 – Q4
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
LOGIC DIAGRAM
DATA
Q
Q
ENABLE
TO OTHER LATCH
SN54/74LS375
4-BIT D LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
1
7
9
15
4
12
E0,1
D0
D1
E2,3
Q0
Q1
D2
Q2
D3
Q3
2
3
6 5 10 11 14 13
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-528